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| author | Claire Wolf <clifford@clifford.at> | 2020-01-30 18:01:13 +0100 |
|---|---|---|
| committer | Claire Wolf <clifford@clifford.at> | 2020-01-30 18:01:13 +0100 |
| commit | 23c44afaed7c3fb97b01ca241731fc84dd03d5a7 (patch) | |
| tree | 116af0e63b957a096bf5f6bfb562cc672b32f517 /frontends | |
| parent | 1679682fa3ae18282b49452891282901a3548ecc (diff) | |
| download | yosys-23c44afaed7c3fb97b01ca241731fc84dd03d5a7.tar.gz yosys-23c44afaed7c3fb97b01ca241731fc84dd03d5a7.tar.bz2 yosys-23c44afaed7c3fb97b01ca241731fc84dd03d5a7.zip | |
Add Verific support for OPER_REDUCE_NAND
Signed-off-by: Claire Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 9274cf5ca..8a99f19b9 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -539,6 +539,14 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr return true; } + if (inst->Type() == OPER_REDUCE_NAND) { + Wire *tmp = module->addWire(NEW_ID); + cell = module->addReduceAnd(inst_name, IN, tmp, SIGNED); + module->addNot(NEW_ID, tmp, net_map_at(inst->GetOutput())); + import_attributes(cell->attributes, inst); + return true; + } + if (inst->Type() == OPER_REDUCE_OR) { cell = module->addReduceOr(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED); import_attributes(cell->attributes, inst); |