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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 21:45:27 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 21:45:27 -0800 |
| commit | 2c65e1abacc4401c4fd3e9b48f52c4de120bc511 (patch) | |
| tree | c6c70b415aa68e971292462e1b71f11a4bc89736 /frontends | |
| parent | a2c4d98da70744253ccbe253083ef9df5fa39305 (diff) | |
| download | yosys-2c65e1abacc4401c4fd3e9b48f52c4de120bc511.tar.gz yosys-2c65e1abacc4401c4fd3e9b48f52c4de120bc511.tar.bz2 yosys-2c65e1abacc4401c4fd3e9b48f52c4de120bc511.zip | |
abc9: break SCC by setting (* keep *) on output wires
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index b4304a581..f4decaf25 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -831,6 +831,7 @@ void AigerReader::post_process() } else { wire->port_output = false; + existing->port_output = true; module->connect(wire, existing); wire = existing; } @@ -845,8 +846,9 @@ void AigerReader::post_process() wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index); } else { - module->connect(wire, existing); wire->port_output = false; + existing->port_output = true; + module->connect(wire, existing); } log_debug(" -> %s\n", log_id(indexed_name)); } |