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* Added $anyconst and $aconstClifford Wolf2016-07-273-1/+50
* Added "read_verilog -dump_rtlil"Clifford Wolf2016-07-273-9/+30
* Fixed a verilog parser memory leakClifford Wolf2016-07-251-0/+1
* Fixed parsing of empty positional cell portsClifford Wolf2016-07-251-2/+31
* No tristate warning message for "read_verilog -lib"Clifford Wolf2016-07-233-8/+11
* Using $initstate in "initial assume" and "initial assert"Clifford Wolf2016-07-211-1/+6
* Added $initstate cell type and vlog functionClifford Wolf2016-07-212-0/+26
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-216-12/+16
* Added basic support for $expect cellsClifford Wolf2016-07-136-8/+25
* Fixed mem assignment in left-hand-side concatenationClifford Wolf2016-07-081-0/+44
* Allow defining input ports as "input logic" in SystemVerilogRuben Undheim2016-06-201-2/+2
* Merge branch 'sv_packages' of https://github.com/rubund/yosysClifford Wolf2016-06-195-1/+49
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| * A few modifications after pull request commentsRuben Undheim2016-06-181-2/+2
| * Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-185-1/+49
* | Added "read_blif -sop"Clifford Wolf2016-06-181-5/+10
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* Added $sop cell type and "abc -sop"Clifford Wolf2016-06-172-24/+80
* Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}Clifford Wolf2016-05-271-0/+11
* Fixed access-after-delete bug in mem2reg codeClifford Wolf2016-05-272-6/+23
* fixed typos in error messagesClifford Wolf2016-05-271-3/+3
* Small improvements in Verilog front-end docsClifford Wolf2016-05-201-0/+3
* Include <cmath> in yosys.hClifford Wolf2016-05-081-9/+0
* Added support for "active high" and "active low" latches in BLIF front-endClifford Wolf2016-04-221-0/+4
* Added "yosys -D" featureClifford Wolf2016-04-217-8/+8
* Fixed handling of parameters and const functions in casex/casez patternClifford Wolf2016-04-215-8/+37
* Do not set "nosync" on task outputs, fixes #134Clifford Wolf2016-03-241-1/+2
* Added support for $stop system taskClifford Wolf2016-03-211-5/+5
* Added $display %m support, fixed mem leak in $display, fixes #128Clifford Wolf2016-03-191-20/+44
* Fixed localparam signdness, fixes #127Clifford Wolf2016-03-181-1/+1
* Set "nosync" attribute on internal task/function wiresClifford Wolf2016-03-181-0/+1
* Fixed Verilog parser fix and more similar improvementsClifford Wolf2016-03-151-18/+9
* Use left-recursive rule for cell_port_list in Verilog parser.Andrew Becker2016-03-151-6/+10
* Fixed typos in verilog_defaults help messageClifford Wolf2016-03-101-3/+3
* Fixed BLIF parser for empty port assignmentsClifford Wolf2016-02-241-2/+2
* Fixed some visual studio warningsClifford Wolf2016-02-133-4/+4
* Support for more Verific primitives (patch I got per email)Clifford Wolf2016-02-131-1/+31
* Bugfix in Verific front-endClifford Wolf2016-02-031-2/+5
* Updated verific build instructionsClifford Wolf2016-02-021-2/+0
* Added addBufGate module methodClifford Wolf2016-02-021-0/+5
* genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSi...Rick Altherr2016-01-311-3/+3
* Various improvements in BLIF front-endClifford Wolf2015-12-202-41/+86
* Fixed oom bug in ilang parserClifford Wolf2015-11-291-2/+2
* Fixed performance bug in ilang parserClifford Wolf2015-11-271-6/+12
* Added PRIM_DLATCHRS support to verific front-endClifford Wolf2015-11-241-0/+10
* Fixed handling of re-declarations of wires in tasks and functionsClifford Wolf2015-11-231-7/+26
* Fixed performance bug in Verific importerClifford Wolf2015-11-161-10/+12
* Changes for Verific 3.16_484_32_151112Clifford Wolf2015-11-122-3/+6
* More bugfixes in handling of parameters in tasks and functionsClifford Wolf2015-11-121-1/+11
* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-113-4/+9
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-254-38/+38
* Fixed bug in verilog parserClifford Wolf2015-10-151-1/+1
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