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* Support asymmetric memories for verific frontendMiodrag Milanovic2020-06-011-6/+1
* Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logicclairexen2020-05-291-2/+2
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| * ast/simplify: don't bitblast async ROMs declared as `logic`.whitequark2020-05-051-2/+2
* | Merge pull request #2097 from whitequark/ilang_lexer-fix-erangewhitequark2020-05-291-1/+3
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| * | ilang_lexer: fix check for out of range literal.whitequark2020-05-291-1/+3
* | | Merge pull request #2033 from boqwxp/cleanup-verilog-lexerwhitequark2020-05-291-6/+5
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| * | verilog: Move lexer location variables from global namespace to `VERILOG_FRON...Alberto Gonzalez2020-05-061-6/+5
* | | Silence spurious warning in Verilog lexer when compiling with GCCRupert Swarbrick2020-05-261-1/+3
* | | verilog: move attr from simple_behav_stmt to its children to attachEddie Hung2020-05-251-13/+17
* | | verilog: do not warn for attributes on null statementsEddie Hung2020-05-251-2/+0
* | | verilog: handle empty generate statement by removing gen_stmt_or_null...Eddie Hung2020-05-251-7/+8
* | | verilog: fix #2037 by permitting (and freeing) attributes on null stmtEddie Hung2020-05-251-1/+5
* | | Merge pull request #2057 from YosysHQ/eddie/fix_task_attrEddie Hung2020-05-211-11/+9
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| * | | Update frontends/verilog/verilog_parser.yEddie Hung2020-05-211-1/+1
| * | | verilog: attributes before task enable (but 13 s/r conflicts)Eddie Hung2020-05-141-10/+8
* | | | Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-1/+20
* | | | Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dffEddie Hung2020-05-182-4/+12
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| * | | | aiger: -xaiger to return $_FF_ flopsEddie Hung2020-05-141-15/+2
| * | | | aiger/xaiger: use odd for negedge clk, even for posedgeEddie Hung2020-05-141-4/+3
| * | | | aiger: -xaiger to parse initial state back into (* init *) on Q wireEddie Hung2020-05-141-1/+2
| * | | | aiger: -xaiger to read $_DFF_[NP]_ back with new clocks createdEddie Hung2020-05-142-3/+24
* | | | | Revert "Add support for non-power-of-two mem chunks in verific importer"Claire Wolf2020-05-171-12/+2
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* | | | Merge pull request #2045 from YosysHQ/eddie/fix2042Eddie Hung2020-05-141-1/+13
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| * | | | verilog: default to input in sv mode if task/func has no dir ...Eddie Hung2020-05-131-2/+10
| * | | | verilog: error out when non-ANSI task/func argumentsEddie Hung2020-05-111-1/+5
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* | | | Merge pull request #2052 from YosysHQ/claire/verific_memfixClaire Wolf2020-05-141-2/+12
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| * | | | Add support for non-power-of-two mem chunks in verific importerClaire Wolf2020-05-141-2/+12
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* | | | Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-141-1/+1
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| * | | ast: swap range regardless of range_left >= 0Eddie Hung2020-05-041-1/+1
* | | | Merge pull request #2022 from Xiretza/fallthroughswhitequark2020-05-082-4/+5
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| * | | | Add YS_FALLTHROUGH macro to mark case fall-throughXiretza2020-05-072-4/+5
* | | | | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-075-16/+82
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| * | | | Fix handling of signed indices in bit slicesClaire Wolf2020-05-021-3/+8
| * | | | Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-025-7/+22
| * | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offs...Claire Wolf2020-05-024-7/+53
* | | | | Merge pull request #2028 from zachjs/masterEddie Hung2020-05-061-1/+6
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| * | | | verilog: allow null gen-if then blockZachary Snow2020-05-061-1/+6
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* | | | Merge pull request #2025 from YosysHQ/eddie/frontend_cleanupEddie Hung2020-05-056-31/+31
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| * | | | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-046-31/+31
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* | | | Merge pull request #2024 from YosysHQ/eddie/primitive_srcEddie Hung2020-05-052-2/+6
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| * | | | verilog: set src attribute for primitivesEddie Hung2020-05-042-2/+6
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* / / / verilog: fix specify src attributeEddie Hung2020-05-041-18/+20
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* | | Merge pull request #1996 from boqwxp/rtlil_source_locationsEddie Hung2020-05-041-13/+13
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| * | frontend: Include complete source location instead of just `location.first_li...Alberto Gonzalez2020-05-011-13/+13
* | | aiger: fixes for ports that have start_offset != 0Eddie Hung2020-05-021-30/+47
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* | Merge pull request #2001 from whitequark/wasiwhitequark2020-05-011-1/+1
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| * | Add WASI platform support.whitequark2020-04-301-1/+1
* | | Merge pull request #1981 from YosysHQ/claire/fix1837Claire Wolf2020-05-011-0/+4
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| * | Clear current_scope when done with RTLIL generation, fixes #1837Claire Wolf2020-04-221-0/+4
* | | verific: ignore anonymous enumsEddie Hung2020-04-301-1/+4
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