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authorEddie Hung <eddie@fpgeh.com>2020-05-11 10:20:33 -0700
committerEddie Hung <eddie@fpgeh.com>2020-05-25 07:36:53 -0700
commit88bddb37c91e8fe136e5c9cc2ade20fadccd1946 (patch)
treed6a822ef14477b462f84ff675e7ffc890936839a /frontends
parentd21a07c7b5ef57de5428e5f7913338af582146b5 (diff)
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verilog: handle empty generate statement by removing gen_stmt_or_null...
... rule which causes a s/r conflict. Now we get an empty genblock, which should be okay.
Diffstat (limited to 'frontends')
-rw-r--r--frontends/verilog/verilog_parser.y15
1 files changed, 8 insertions, 7 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index a0250439e..eb7e136ae 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2440,7 +2440,7 @@ gen_case_item:
} case_select {
case_type_stack.push_back(0);
SET_AST_NODE_LOC(ast_stack.back(), @2, @2);
- } gen_stmt_or_null {
+ } gen_stmt_block {
case_type_stack.pop_back();
ast_stack.pop_back();
};
@@ -2532,7 +2532,11 @@ module_gen_body:
/* empty */;
gen_stmt_or_module_body_stmt:
- gen_stmt | module_body_stmt;
+ gen_stmt | module_body_stmt |
+ attr ';' {
+ log_file_warning(current_filename, get_line_num(), "Attribute(s) attached to null statement. Ignoring.\n");
+ free_attr($1);
+ };
// this production creates the obligatory if-else shift/reduce conflict
gen_stmt:
@@ -2554,7 +2558,7 @@ gen_stmt:
AstNode *block = new AstNode(AST_GENBLOCK);
ast_stack.back()->children.push_back(block);
ast_stack.push_back(block);
- } gen_stmt_or_null {
+ } gen_stmt_block {
ast_stack.pop_back();
} opt_gen_else {
SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
@@ -2604,11 +2608,8 @@ gen_stmt_block:
ast_stack.pop_back();
};
-gen_stmt_or_null:
- gen_stmt_block | ';';
-
opt_gen_else:
- TOK_ELSE gen_stmt_or_null | /* empty */ %prec FAKE_THEN;
+ TOK_ELSE gen_stmt_block | /* empty */ %prec FAKE_THEN;
expr:
basic_expr {