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Merge pull request #3568 from YosysHQ/verific_msg
Miodrag Milanović
2022-12-05
1
-3
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+16
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set VERI-1063 explicitly
Miodrag Milanovic
2022-12-02
1
-5
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+7
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Set all verific messages of certain type to other
Miodrag Milanovic
2022-11-30
1
-3
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+14
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Merge pull request #3569 from YosysHQ/ver_no_rewriters
Miodrag Milanović
2022-12-05
1
-0
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+2
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reset elaboration error after rewriter
Miodrag Milanovic
2022-11-30
1
-0
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+2
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Merge pull request #3551 from daglem/struct-array-swapped-range
Jannis Harder
2022-12-01
2
-21
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+61
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Added asserts for current limitation of array dimensions in packed structs
Dag Lem
2022-11-30
1
-0
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+8
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Check for all cases of currently unsupported array dimensions in packed structs
Dag Lem
2022-11-30
1
-10
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+13
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Support for swapped ranges in second array dimension
Dag Lem
2022-11-23
1
-3
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+10
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Support for arrays with swapped ranges within structs
Dag Lem
2022-11-12
2
-10
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+32
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update documentation
Miodrag Milanovic
2022-11-25
1
-3
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+3
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Support importing verilog configurations using Verific
Miodrag Milanovic
2022-11-25
2
-4
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+39
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Merge pull request #3552 from daglem/fix-sv-c-array-dimensions
Jannis Harder
2022-11-23
1
-3
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+3
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Correct interpretation of SystemVerilog C-style array dimensions
Dag Lem
2022-11-13
1
-3
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+3
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Merge branch 'zachjs-master'
Jannis Harder
2022-11-21
1
-0
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+4
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verilog: Support module-scoped task/function calls
Zachary Snow
2022-10-29
1
-0
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+4
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Add additional help info
Miodrag Milanovic
2022-10-31
1
-0
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+2
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Enable importing blackbox modules only
Miodrag Milanovic
2022-10-31
1
-1
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+33
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Support for reading liberty files using verific
Miodrag Milanovic
2022-10-31
1
-1
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+45
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Skip verific primitives and operators import by default
Miodrag Milanovic
2022-10-14
1
-0
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+1
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Add option to import all cells from all libraries
Miodrag Milanovic
2022-10-14
1
-1
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+30
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fix whitespace
Miodrag Milanovic
2022-10-10
1
-1
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+1
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Merge pull request #3452 from ALGCDG/master
Miodrag Milanović
2022-10-10
1
-1
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+8
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Changing error reason string to be based on lut input plane limit constant.
Archie
2022-10-02
1
-1
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+1
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Adding check for BLIF names command input plane size.
Archie
2022-08-21
1
-1
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+8
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Fix handling of verific -L options, add implicit "-L work"
Claire Xenia Wolf
2022-10-10
1
-0
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+14
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Add support for EDIF file reading using Verific
Miodrag Milanovic
2022-10-04
1
-1
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+47
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support file content redirection for verific frontened
Miodrag Milanovic
2022-09-28
1
-14
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+60
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Add comment for future self
Miodrag Milanovic
2022-09-28
1
-0
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+7
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Handle attributes imported from verific
Miodrag Milanovic
2022-09-28
1
-5
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+24
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Import memory attributes
Miodrag Milanovic
2022-09-21
1
-0
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+1
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verific: better fix for read callback
Miodrag Milanovic
2022-09-07
1
-5
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+3
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verific: fix crash when using prep right after read
Miodrag Milanovic
2022-09-07
1
-0
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+3
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Fitting help messages to 80 character width
KrystalDelusion
2022-08-24
1
-6
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+6
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set default_nettype to wire for resetall
Miodrag Milanovic
2022-08-10
1
-0
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+1
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resetall does not affect text defines, but undefineall does
Miodrag Milanovic
2022-08-10
1
-0
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+4
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Encode filename unprintable chars
Miodrag Milanovic
2022-08-08
3
-27
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+27
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verific - make filepath handling compatible with verilog frontend
Miodrag Milanovic
2022-08-08
1
-15
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+29
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Merge pull request #3089 from YosysHQ/gatecat/liberty_wb
Miodrag Milanović
2022-08-01
1
-0
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+14
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Add read_liberty -wb
gatecat
2021-11-25
1
-0
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+14
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Setting wire upto in verific import
Miodrag Milanovic
2022-07-29
1
-2
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+5
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Update README
Miodrag Milanović
2022-07-28
1
-1
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+1
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Upadte documentation and changelog
Miodrag Milanovic
2022-07-04
1
-0
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+1
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Update to new verific extensions inteface
Miodrag Milanovic
2022-06-30
1
-3
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+29
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Add check for BLIF with no model name
Archie
2022-06-22
1
-1
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+4
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Revert "use new verific extensions library"
Miodrag Milanovic
2022-06-21
1
-70
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+54
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use new verific extensions library
Miodrag Milanovic
2022-06-17
1
-54
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+70
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removed deprecated features code
Miodrag Milanovic
2022-06-13
1
-235
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+0
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verific: Added "-vlog-libext" option to specify search extension for libraries
Miodrag Milanovic
2022-06-09
1
-1
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+16
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verific: proper file location for readmem commands
Miodrag Milanovic
2022-06-04
1
-0
/
+33
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