Support importing verilog configurations using Verific

2 files changed, 39 insertions, 4 deletions

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 6ef563929..1eab9931f 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -47,6 +47,7 @@ USING_YOSYS_NAMESPACE
 #include "VeriModule.h"
 #include "VeriWrite.h"
 #include "VeriLibrary.h"
+#include "VeriExpression.h"
 
 #ifdef VERIFIC_VHDL_SUPPORT
 #include "vhdl_file.h"
@@ -2267,7 +2268,7 @@ struct VerificExtNets
 	}
 };
 
-void verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top)
+std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top)
 {
 	verific_sva_fsm_limit = 16;
 
@@ -2300,6 +2301,18 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
 			VeriModule *veri_module = veri_lib->GetModule(top.c_str(), 1);
 			if (veri_module) {
 				veri_modules.InsertLast(veri_module);
+				if (veri_module->IsConfiguration()) {
+					VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
+					VeriName *module_name = (VeriName*)cfg->GetTopModuleNames()->GetLast();
+					VeriLibrary *lib = veri_module->GetLibrary() ;
+					if (module_name && module_name->IsHierName()) {
+						VeriName *prefix = module_name->GetPrefix() ;
+						const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
+						if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
+					}
+					veri_module = (lib && module_name) ? lib->GetModule(module_name->GetName(), 1) : 0;
+					top = veri_module->GetName();
+				}
 			}
 
 			// Also elaborate all root modules since they may contain bind statements
@@ -2378,6 +2391,7 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
 
 	if (!verific_error_msg.empty())
 		log_error("%s\n", verific_error_msg.c_str());
+	return top;
 }
 
 YOSYS_NAMESPACE_END
@@ -3246,8 +3260,29 @@ struct VerificPass : public Pass {
 
 					VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
 					if (veri_module) {
-						log("Adding Verilog module '%s' to elaboration queue.\n", name);
-						veri_modules.InsertLast(veri_module);
+						if (veri_module->IsConfiguration()) {
+							log("Adding Verilog configuration '%s' to elaboration queue.\n", name);	
+							veri_modules.InsertLast(veri_module);
+
+							top_mod_names.erase(name);
+
+							VeriConfiguration *cfg = (VeriConfiguration*)veri_module;
+							VeriName *module_name;
+							int i;
+							FOREACH_ARRAY_ITEM(cfg->GetTopModuleNames(), i, module_name) {
+								VeriLibrary *lib = veri_module->GetLibrary() ;
+								if (module_name && module_name->IsHierName()) {
+									VeriName *prefix = module_name->GetPrefix() ;
+									const char *lib_name = (prefix) ? prefix->GetName() : 0 ;
+									if (!Strings::compare("work", lib_name)) lib = veri_file::GetLibrary(lib_name, 1) ;
+								}
+								veri_module = (lib && module_name) ? lib->GetModule(module_name->GetName(), 1) : 0;
+								top_mod_names.insert(veri_module->GetName());
+							}
+						} else {
+							log("Adding Verilog module '%s' to elaboration queue.\n", name);
+							veri_modules.InsertLast(veri_module);
+						}
 						continue;
 					}
 #ifdef VERIFIC_VHDL_SUPPORT
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h
index 695c04f3b..d9f0077db 100644
--- a/frontends/verific/verific.h
+++ b/frontends/verific/verific.h
@@ -26,7 +26,7 @@ YOSYS_NAMESPACE_BEGIN
 extern int verific_verbose;
 
 extern bool verific_import_pending;
-extern void verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top = std::string());
+extern std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top = std::string());
 
 extern pool<int> verific_sva_prims;