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authorArchie <ac11018@ic.ac.uk>2022-08-21 23:18:20 -0500
committerArchie <ac11018@ic.ac.uk>2022-08-21 23:18:20 -0500
commit15a0697c70e14d6277e26f6fa21898be5a8f6ff8 (patch)
treeb3429075ae105278dbd6f06efabdf49834385870 /frontends
parentdb73f3c26b2768f93c7573b7c7d74b1cc7a0756d (diff)
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Adding check for BLIF names command input plane size.
Diffstat (limited to 'frontends')
-rw-r--r--frontends/blif/blifparse.cc9
1 files changed, 8 insertions, 1 deletions
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index 73d1f0ea7..52742660e 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -21,6 +21,8 @@
YOSYS_NAMESPACE_BEGIN
+const int lut_input_plane_limit = 12;
+
static bool read_next_line(char *&buffer, size_t &buffer_size, int &line_count, std::istream &f)
{
string strbuf;
@@ -513,6 +515,11 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
sopmode = -1;
lastcell = sopcell;
}
+ else if (input_sig.size() > lut_input_plane_limit)
+ {
+ err_reason = stringf("names' input plane must have fewer than 13 signals.");
+ goto error_with_reason;
+ }
else
{
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
@@ -576,7 +583,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (lutptr)
{
- if (input_len > 12)
+ if (input_len > lut_input_plane_limit)
goto error;
for (int i = 0; i < (1 << input_len); i++) {