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| author | Dag Lem <dag@nimrod.no> | 2022-11-13 07:41:25 +0100 |
|---|---|---|
| committer | Dag Lem <dag@nimrod.no> | 2022-11-13 07:41:25 +0100 |
| commit | a862642fac5d5b7700b2e13829a411f2755273a0 (patch) | |
| tree | 0229fc5566a4035b244ca3bcae4068949da67811 /frontends | |
| parent | 553eb6ac1eb49085f979d7650d83b3b93298835a (diff) | |
| download | yosys-a862642fac5d5b7700b2e13829a411f2755273a0.tar.gz yosys-a862642fac5d5b7700b2e13829a411f2755273a0.tar.bz2 yosys-a862642fac5d5b7700b2e13829a411f2755273a0.zip | |
Correct interpretation of SystemVerilog C-style array dimensions
IEEE Std 1800™-2017 7.4.2 specifies that [size] is the same as [0:size-1].
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index c533b0c40..70ee47561 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -229,9 +229,9 @@ static AstNode *checkRange(AstNode *type_node, AstNode *range_node) static void rewriteRange(AstNode *rangeNode) { if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) { - // SV array size [n], rewrite as [n-1:0] - rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true)); - rangeNode->children.push_back(AstNode::mkconst_int(0, false)); + // SV array size [n], rewrite as [0:n-1] + rangeNode->children.push_back(new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true))); + rangeNode->children[0] = AstNode::mkconst_int(0, false); } } |