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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-10-31 18:04:34 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-10-31 18:04:34 +0100 |
| commit | 59b6ac47c9121278c9259b82c68b38477ccb73ad (patch) | |
| tree | df151dca3ce9039c95d38743b37efae78806f49c /frontends | |
| parent | 6fb80bce1577e298fb25e387beb1ff5fb6c7c53e (diff) | |
| download | yosys-59b6ac47c9121278c9259b82c68b38477ccb73ad.tar.gz yosys-59b6ac47c9121278c9259b82c68b38477ccb73ad.tar.bz2 yosys-59b6ac47c9121278c9259b82c68b38477ccb73ad.zip | |
Add additional help info
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index fb5fc0c6c..6ef563929 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2439,6 +2439,8 @@ struct VerificPass : public Pass { log(" verific {-liberty} <liberty-file>..\n"); log("\n"); log("Load the specified Liberty files into Verific.\n"); + log("Default library when -work is not present is one specified in liberty file.\n"); + log("To use from SystemVerilog or VHDL use -L to specify liberty library."); log("\n"); log(" -lib\n"); log(" only create empty blackbox modules\n"); |