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* | Add statement labels for immediate assertionsClifford Wolf2018-04-131-18/+21
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Allow "property" in immediate assertionsClifford Wolf2018-04-121-17/+20
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add read_verilog anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-1/+33
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-271-2/+167
|/ | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Verilog "automatic" keyword (ignored in synthesis)Clifford Wolf2017-11-231-13/+17
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* Accept real-valued delay valuesClifford Wolf2017-11-181-0/+1
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* Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the ↵Udi Finkelstein2017-09-301-3/+5
| | | | | | textbook solution (Oreilly 'Flex & Bison' page 189)
* Fix ignoring of simulation timings so that invalid module parameters cause ↵Clifford Wolf2017-09-261-0/+2
| | | | syntax errors
* Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵Clifford Wolf2017-06-071-0/+1
| | | | const reg"
* Fix handling of Verilog ~& and ~| operatorsClifford Wolf2017-06-011-0/+8
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* Add support for localparam in module headerClifford Wolf2017-04-301-1/+7
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* Allow $anyconst, etc. in non-formal SV modeClifford Wolf2017-03-011-1/+1
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* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-1/+25
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* Add support for SystemVerilog unique, unique0, and priority caseClifford Wolf2017-02-231-4/+21
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* Added SystemVerilog support for ++ and --Clifford Wolf2017-02-231-0/+9
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* Add checker support to verilog front-endClifford Wolf2017-02-091-2/+13
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* Add SV "rand" and "const rand" supportClifford Wolf2017-02-081-6/+24
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* Further improve cover() supportClifford Wolf2017-02-041-0/+6
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* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-1/+7
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* Add "enum" and "typedef" lexer supportClifford Wolf2017-01-171-1/+1
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* Added support for hierarchical defparamsClifford Wolf2016-11-151-3/+2
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* Added $anyseq cell typeClifford Wolf2016-10-141-1/+1
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* Removed $aconst cell typeClifford Wolf2016-08-301-1/+1
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* Removed $predict againClifford Wolf2016-08-281-7/+1
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* Added read_verilog -norestrict -assume-assertsClifford Wolf2016-08-261-3/+16
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* Improved verilog parser errorsClifford Wolf2016-08-251-0/+3
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* Fixed bug in parsing real constantsClifford Wolf2016-08-061-4/+4
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* Added $anyconst and $aconstClifford Wolf2016-07-271-1/+1
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* Fixed a verilog parser memory leakClifford Wolf2016-07-251-0/+1
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* Fixed parsing of empty positional cell portsClifford Wolf2016-07-251-2/+31
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* No tristate warning message for "read_verilog -lib"Clifford Wolf2016-07-231-5/+5
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* Added $initstate cell type and vlog functionClifford Wolf2016-07-211-0/+2
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* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-5/+5
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* Added basic support for $expect cellsClifford Wolf2016-07-131-1/+8
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* Allow defining input ports as "input logic" in SystemVerilogRuben Undheim2016-06-201-2/+2
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* Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-181-0/+29
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* Fixed handling of parameters and const functions in casex/casez patternClifford Wolf2016-04-211-2/+6
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* Fixed Verilog parser fix and more similar improvementsClifford Wolf2016-03-151-18/+9
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* Use left-recursive rule for cell_port_list in Verilog parser.Andrew Becker2016-03-151-6/+10
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* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-111-1/+1
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* Fixed bug in verilog parserClifford Wolf2015-10-151-1/+1
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* Added support for "parameter" and "localparam" in global contextClifford Wolf2015-10-071-0/+2
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* Fixed detection of "task foo(bar);" syntax errorClifford Wolf2015-09-221-0/+2
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* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-121-1/+1
| | | | This is based on work done by Larry Doolittle
* Fixed trailing whitespacesClifford Wolf2015-07-021-5/+5
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* Added non-std verilog assume() statementClifford Wolf2015-02-261-2/+8
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* Parser support for complex delay expressionsClifford Wolf2015-02-201-7/+20
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* YosysJS stuffClifford Wolf2015-02-191-0/+1
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* Improved read_verilog support for empty behavioral statementsClifford Wolf2015-02-101-6/+2
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