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| author | Andrew Becker <andrew.becker@epfl.ch> | 2016-03-14 19:28:34 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-03-15 12:03:40 +0100 |
| commit | 81d4e9e7c1c311f837dadb1634c83b4e70929669 (patch) | |
| tree | 868cecfa8e060a8308977470ebd9e2812e7d6ce4 /frontends/verilog/verilog_parser.y | |
| parent | 2a8d5e64f5a994fa8f4f51c00d647ad977e42e4b (diff) | |
| download | yosys-81d4e9e7c1c311f837dadb1634c83b4e70929669.tar.gz yosys-81d4e9e7c1c311f837dadb1634c83b4e70929669.tar.bz2 yosys-81d4e9e7c1c311f837dadb1634c83b4e70929669.zip | |
Use left-recursive rule for cell_port_list in Verilog parser.
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 863fee599..7849757ec 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -801,14 +801,14 @@ single_cell: astbuf2->str = *$1; delete $1; ast_stack.back()->children.push_back(astbuf2); - } '(' cell_port_list ')' | + } '(' cell_port_list_opt ')' | TOK_ID non_opt_range { astbuf2 = astbuf1->clone(); if (astbuf2->type != AST_PRIMITIVE) astbuf2->str = *$1; delete $1; ast_stack.back()->children.push_back(new AstNode(AST_CELLARRAY, $2, astbuf2)); - } '(' cell_port_list ')'; + } '(' cell_port_list_opt ')'; prim_list: single_prim | @@ -819,7 +819,7 @@ single_prim: /* no name */ { astbuf2 = astbuf1->clone(); ast_stack.back()->children.push_back(astbuf2); - } '(' cell_port_list ')'; + } '(' cell_port_list_opt ')'; cell_parameter_list_opt: '#' '(' cell_parameter_list ')' | /* empty */; @@ -842,14 +842,18 @@ cell_parameter: delete $2; }; -cell_port_list: - /* empty */ | cell_port | - cell_port ',' cell_port_list | +cell_port_list_opt: + /* empty */ | + cell_port_list | /* empty */ ',' { AstNode *node = new AstNode(AST_ARGUMENT); astbuf2->children.push_back(node); } cell_port_list; +cell_port_list: + cell_port | + cell_port_list ',' cell_port; + cell_port: expr { AstNode *node = new AstNode(AST_ARGUMENT); |