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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2016-06-20 20:16:37 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2016-06-20 20:16:37 +0200 |
| commit | 545bcb37e8fa569d88374f92aafdcc1004e9b587 (patch) | |
| tree | 8df204605907e01759969afa2386274ea398c620 /frontends/verilog/verilog_parser.y | |
| parent | 541083cf329addb57117618de41697dd010d07cf (diff) | |
| download | yosys-545bcb37e8fa569d88374f92aafdcc1004e9b587.tar.gz yosys-545bcb37e8fa569d88374f92aafdcc1004e9b587.tar.bz2 yosys-545bcb37e8fa569d88374f92aafdcc1004e9b587.zip | |
Allow defining input ports as "input logic" in SystemVerilog
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index b46cdd38f..e7c3578c7 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -311,7 +311,7 @@ module_arg: node->children.push_back($3); if (!node->is_input && !node->is_output) frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str()); - if (node->is_reg && node->is_input && !node->is_output) + if (node->is_reg && node->is_input && !node->is_output && !sv_mode) frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str()); ast_stack.back()->children.push_back(node); append_attr(node, $1); @@ -764,7 +764,7 @@ wire_name: if (port_stubs.count(*$1) != 0) { if (!node->is_input && !node->is_output) frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str()); - if (node->is_reg && node->is_input && !node->is_output) + if (node->is_reg && node->is_input && !node->is_output && !sv_mode) frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str()); node->port_id = port_stubs[*$1]; port_stubs.erase(*$1); |