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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-26 01:52:59 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-26 01:52:59 +0200 |
| commit | 2cc09161ffd774430293dfd18e307e75bea73c5e (patch) | |
| tree | 9c018ea7954daddaaa8e6cc89502ed522f3a30a9 /frontends/verilog/verilog_parser.y | |
| parent | 143c0abd33ed76b2a7e38dbbac1767e6f7edd68f (diff) | |
| download | yosys-2cc09161ffd774430293dfd18e307e75bea73c5e.tar.gz yosys-2cc09161ffd774430293dfd18e307e75bea73c5e.tar.bz2 yosys-2cc09161ffd774430293dfd18e307e75bea73c5e.zip | |
Fix ignoring of simulation timings so that invalid module parameters cause syntax errors
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index c5ff3d402..9fa2a1a2f 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -355,6 +355,8 @@ package_body_stmt: localparam_decl; non_opt_delay: + '#' TOK_ID { delete $2; } | + '#' TOK_CONSTVAL { delete $2; } | '#' '(' expr ')' { delete $3; } | '#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; }; |