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* verilog: Support void functionsJannis Harder2023-03-201-1/+18
| | | | | | | The difference between void functions and tasks is that always_comb's implicit sensitivity list behaves as if functions were inlined, but ignores signals read only in tasks. This only matters for event based simulation, and for synthesis we can treat a void function like a task.
* Resolve struct member package typesDag Lem2023-01-291-0/+7
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* Correct interpretation of SystemVerilog C-style array dimensionsDag Lem2022-11-131-3/+3
| | | | IEEE Std 1800™-2017 7.4.2 specifies that [size] is the same as [0:size-1].
* verilog: support for time scale delay valuesZachary Snow2022-02-141-1/+4
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* Specify minimum bison version 3.0+Zachary Snow2021-10-011-0/+2
| | | | | | | | | Yosys works with bison 3.0 (or newer), but not bison 2.7 (the previous release). Ideally, we would require "3" rather than "3.0" to give a better error message, but bison 2.3, which still ships with macOS, does not support major-only version requirements. With this change, building with an outdated bison yields: `frontends/rtlil/rtlil_parser.y:25.10-14: require bison 3.0, but have 2.3`.
* Merge pull request #3014 from YosysHQ/claire/fix-vgtestClaire Xen2021-09-241-0/+1
|\ | | | | Fix "make vgtest"
| * Fix TOK_ID memory leak in for_initializationZachary Snow2021-09-231-0/+1
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* | sv: support wand and wor of data typesZachary Snow2021-09-211-9/+12
| | | | | | | | | | | | This enables the usage of declarations of wand or wor with a base type of logic, integer, or a typename. Note that declarations of nets with 2-state base types is still permitted, in violation of the spec.
* | verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-211-0/+1
|/ | | | | | | | - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
* sv: support declaration in generate for initializationZachary Snow2021-08-311-1/+95
| | | | | | | | This is accomplished by generating a unique name for the genvar, renaming references to the genvar only in the loop's initialization, guard, and incrementation, and finally adding a localparam inside the loop body with the original name so that the genvar can be shadowed as expected.
* sv: support declaration in procedural for initializationZachary Snow2021-08-301-1/+48
| | | | | In line with other tools, this adds an extra wrapping block around such for loops to appropriately scope the variable.
* sv: improve support for wire and var with user-defined typesBrett Witherspoon2021-08-121-11/+44
| | | | | | | | | | | | | | | | | - User-defined types must be data types. Using a net type (e.g. wire) is a syntax error. - User-defined types without a net type are always variables (i.e. logic). - Nets and variables can now be explicitly declared using user-defined types: typedef logic [1:0] W; wire W w; typedef logic [1:0] V; var V v; Fixes #2846
* Allow optional comma after last entry in enumMichael Singer2021-08-091-11/+12
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* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-161-3/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This doesn't do anything useful yet: the patch just adds support for the syntax to the lexer and parser and adds some tests to check the syntax parses properly. This generates AST nodes, but doesn't yet generate RTLIL. Since our existing hierarchical_identifier parser doesn't allow bit selects (so you can't do something like foo[1].bar[2].baz), I've also not added support for a trailing bit select (the "constant_bit_select" non-terminal in "bind_target_instance" in the spec). If we turn out to need this in future, we'll want to augment hierarchical_identifier and its other users too. Note that you can't easily use the BNF from the spec: bind_directive ::= "bind" bind_target_scope [ : bind_target_instance_list] bind_instantiation ; | "bind" bind_target_instance bind_instantiation ; even if you fix the lookahead problem, because code like this matches both branches in the BNF: bind a b b_i (.*); The problem is that 'a' could either be a module name or a degenerate hierarchical reference. This seems to be a genuine syntactic ambiguity, which the spec resolves (p739) by saying that we have to wait until resolution time (the hierarchy pass) and take whatever is defined, treating 'a' as an instance name if it names both an instance and a module. To keep the parser simple, it currently accepts this invalid syntax: bind a.b : c d e (.*); This is invalid because we're in the first branch of the BNF above, so the "a.b" term should match bind_target_scope: a module or interface identifier, not an arbitrary hierarchical identifier. This will fail in the hierarchy pass (when it's implemented in a future patch).
* sv: fix a few struct and enum memory leaksZachary Snow2021-07-061-2/+4
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* sv: fix up end label checkingZachary Snow2021-06-161-7/+18
| | | | | | | - disallow [gen]blocks with an end label but not begin label - check validity of module end label - fix memory leak of package name and end label - fix memory leak of module end label
* verilog: fix leaking of type names in parserXiretza2021-06-141-0/+2
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* verilog: fix wildcard port connections leaking memoryXiretza2021-06-141-0/+1
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* verilog: fix leaking ASTNodesXiretza2021-06-141-7/+10
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* verilog: Squash a memory leak.Marcelina Kościelnicka2021-06-141-9/+8
| | | | That was added in ecc22f7fedfa639482dbc55a05709da85116a60f
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* sv: support tasks and functions within packagesZachary Snow2021-06-011-1/+1
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* sv: support remaining assignment operatorsZachary Snow2021-05-251-38/+30
| | | | | - Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>= - Unify existing support for: +=, -=, &=, |=, ^=
* sv: check validity of package end labelZachary Snow2021-05-101-0/+2
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* verilog: check entire user type stack for type definitionXiretza2021-03-211-6/+12
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* sv: allow typenames as function return typesZachary Snow2021-03-191-0/+6
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* sv: support for parameters without default valuesZachary Snow2021-03-021-3/+21
| | | | | | | | | - Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
* verilog: fix sizing of ports with int types in module headersZachary Snow2021-03-011-2/+3
| | | | | | Declaring the ports as standard module items already worked as expected. This adds a missing usage of `checkRange()` so that headers such as `module m(output integer x);` now work correctly.
* sv: extended support for integer typesZachary Snow2021-02-281-39/+69
| | | | | | | | | - Standard data declarations can now use any integer type - Parameters and localparams can now use any integer type - Function returns types can now use any integer type - Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits) - Added longint type (64 bits) - Unified parser source for integer type widths
* Fix handling of unique/unique0/priority cases in the frontend.Marcelina Kościelnicka2021-02-251-14/+15
| | | | | | | | | | Basically: - priority converts to (* full_case *) - unique0 converts to (* parallel_case *) - unique converts to (* parallel_case, full_case *) Fixes #2596.
* Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and ↵TimRudy2021-02-241-2/+7
| | | | turn-off (#2566)
* Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-111-4/+7
|\ | | | | verlog: allow shadowing module ports within generate blocks
| * verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-4/+7
| | | | | | | | | | | | | | | | This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs.
* | Add missing is_signed to type_atomKamil Rakoczy2021-02-111-4/+4
|/ | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Add check of begin/end labels for genblockKamil Rakoczy2021-02-041-0/+2
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: significant block scoping improvementsZachary Snow2021-01-311-17/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* Allow combination of rand and const modifiersZachary Snow2021-01-211-2/+10
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* sv: fix support wire and var data type modifiersZachary Snow2021-01-201-9/+23
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* Parse package user type in module port listLukasz Dalek2021-01-181-30/+32
| | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* sv: complete support for implied task/function port directionsZachary Snow2020-12-311-0/+10
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* Ignore empty parameters in Verilog module instantiationsClaire Xenia Wolf2020-10-011-0/+3
| | | | | | Fixes #2394 Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
* Rewrite multirange arrays sizes [n] as [n-1:0]Lukasz Dalek2020-08-031-2/+11
| | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* Use %precedence in verilog_parser.yClaire Wolf2020-07-151-4/+4
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Fix bison warnings for missing %emptyClaire Wolf2020-07-151-59/+52
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add missing semicolonsKamil Rakoczy2020-07-151-5/+5
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Fix S/R conflictsKamil Rakoczy2020-07-101-1/+2
| | | | | | This commit fixes S/R conflicts introduced by commit 6f9be93. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Fix R/R conflictsKamil Rakoczy2020-07-101-10/+1
| | | | | | | This commit fixes R/R conflicts introduced by commit 7e83a51. Parameter logic is already defined as part of `param_range_type` rule. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Revert "Revert PRs #2203 and #2244."Kamil Rakoczy2020-07-101-10/+19
| | | | This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
* Revert PRs #2203 and #2244.whitequark2020-07-091-19/+10
| | | | | | | | This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15. This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405. This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3. This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68. This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
* Support logic typed parametersLukasz Dalek2020-07-061-7/+10
| | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
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