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* verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Fix read_verilog assert/assume/etc on default case label, fixes ↵Clifford Wolf2019-07-021-0/+2
| | | | | | YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-111-1/+1
| | | | (within always/initial blocks)
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-071-0/+5
|\ | | | | | | clifford/pr983
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-0/+5
| | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | Merge branch 'master' into wandworStefan Biereigel2019-05-271-1/+1
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| * | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-271-1/+1
| | | | | | | | | | | | Includes work from @sumit0190 and @AaronKel
* | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-231-0/+2
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* | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-061-0/+2
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| * \ Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-041-0/+1
| |\ \ | | | | | | | | Add approximate support for SV "var" keyword
| | * | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-041-0/+1
| | |/ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * / Add support for SVA "final" keywordClifford Wolf2019-05-041-0/+1
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve $specrule interfaceClifford Wolf2019-04-231-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add specify parserClifford Wolf2019-04-231-1/+6
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-101-49/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Also add support for labels on sva module items, fixes #699Clifford Wolf20
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-11 15:30:17 +0000
olumn3'>| Signed-off-by: Clifford Wolf <clifford@clifford.at> * Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1 | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> * Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-181-0/+8 |\ | | | | Support for SystemVerilog interfaces and modports | * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+8 | | | | | | | | This time doing the changes mostly in AST before RTLIL generation * | ignore protect endprotectargama2018-10-161-0/+3 |/ * Add "make coverage"Clifford Wolf2018-08-271-1/+1 | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> * Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-151-1/+1 |\ | | | | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test) | * This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-111-1/+1 | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) * | Support more character literalsDan Gisselquist2018-05-031-1/+9 | | * | First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-271-0/+3 |/ | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST * Add Verilog "automatic" keyword (ignored in synthesis)Clifford Wolf2017-11-231-0/+1 | * Fix ignoring of simulation timings so that invalid module parameters cause ↵Clifford Wolf2017-09-261-4/+0 | | | | syntax errors * Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-0/+3 | * Add support for SystemVerilog unique, unique0, and priority caseClifford Wolf2017-02-231-0/+4 | * Added SystemVerilog support for ++ and --Clifford Wolf2017-02-231-1/+3 | * Add checker support to verilog front-endClifford Wolf2017-02-091-9/+11 | * Add SV "rand" and "const rand" supportClifford Wolf2017-02-081-2/+4 | * Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-0/+1 | * Add "enum" and "typedef" lexer supportClifford Wolf2017-01-171-0/+3 | * Removed $predict againClifford Wolf2016-08-281-1/+0 | * Added read_verilog -norestrict -assume-assertsClifford Wolf2016-08-261-1/+1 | * Added SV "restrict" keywordClifford Wolf2016-08-241-1/+2 | * After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-1/+5 | * Added basic support for $expect cellsClifford Wolf2016-07-131-0/+1 | * Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-181-0/+4 | * SystemVerilog also has assume(), added implicit -D FORMALClifford Wolf2015-10-131-1/+1 | * Fixed support for $write system taskClifford Wolf2015-09-231-1/+1 | * Another block of spelling fixesLarry Doolittle2015-08-141-2/+2 | | | | Smaller this time * Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-121-1/+1 | | | | This is based on work done by Larry Doolittle * Fixed trailing whitespacesClifford Wolf2015-07-021-2/+2 | * Ignore celldefine directive in verilog front-endClifford Wolf2015-03-251-0/+3 | * Added non-std verilog assume() statementClifford Wolf2015-02-261-2/+3 | * Fixed handling of "//" in filenames in verilog pre-processorClifford Wolf2015-02-141-0/+4 |
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-11 15:30:17 +0000