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* Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-0/+5
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* | Merge branch 'master' into wandworStefan Biereigel2019-05-271-1/+1
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| * | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-271-1/+1
* | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-231-0/+2
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* | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-061-0/+2
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| * \ Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-041-0/+1
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| | * | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-041-0/+1
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| * / Add support for SVA "final" keywordClifford Wolf2019-05-041-0/+1
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* | Improve $specrule interfaceClifford Wolf2019-04-231-1/+1
* | generated by cgit v1.2.3 (git 2.25.1) at 2025-08-27 18:42:37 +0000 pan class='insertions'>+11
* | Un-break default specify parserClifford Wolf2019-04-231-0/+1
* | Add specify parserClifford Wolf2019-04-231-1/+6
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* Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-101-49/+10
* Also add support for labels on sva module items, fixes #699Clifford Wolf2019-03-081-5/+52
* Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-181-0/+8
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| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+8
* | ignore protect endprotectargama2018-10-161-0/+3
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* Add "make coverage"Clifford Wolf2018-08-271-1/+1
* Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-151-1/+1
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| * This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-111-1/+1
* | Support more character literalsDan Gisselquist2018-05-031-1/+9
* | First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-271-0/+3
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* Add Verilog "automatic" keyword (ignored in synthesis)Clifford Wolf2017-11-231-0/+1
* Fix ignoring of simulation timings so that invalid module parameters cause sy...Clifford Wolf2017-09-261-4/+0
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-0/+3
* Add support for SystemVerilog unique, unique0, and priority caseClifford Wolf2017-02-231-0/+4
* Added SystemVerilog support for ++ and --Clifford Wolf2017-02-231-1/+3
* Add checker support to verilog front-endClifford Wolf2017-02-091-9/+11
* Add SV "rand" and "const rand" supportClifford Wolf2017-02-081-2/+4
* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-0/+1
* Add "enum" and "typedef" lexer supportClifford Wolf2017-01-171-0/+3
* Removed $predict againClifford Wolf2016-08-281-1/+0
* Added read_verilog -norestrict -assume-assertsClifford Wolf2016-08-261-1/+1
* Added SV "restrict" keywordClifford Wolf2016-08-241-1/+2
* After reading the SV spec, using non-standard predict() instead of expect()Clifford Wolf2016-07-211-1/+5
* Added basic support for $expect cellsClifford Wolf2016-07-131-0/+1
* Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-181-0/+4
* SystemVerilog also has assume(), added implicit -D FORMALClifford Wolf2015-10-131-1/+1
* Fixed support for $write system taskClifford Wolf2015-09-231-1/+1
* Another block of spelling fixesLarry Doolittle2015-08-141-2/+2
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-121-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-2/+2
* Ignore celldefine directive in verilog front-endClifford Wolf2015-03-251-0/+3
* Added non-std verilog assume() statementClifford Wolf2015-02-261-2/+3
* Fixed handling of "//" in filenames in verilog pre-processorClifford Wolf2015-02-141-0/+4
* Ignoring more system task and functionsClifford Wolf2015-01-151-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-27 18:42:37 +0000