iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #2179 from splhack/static-cast	clairexen	2020-07-01	1	-0/+2
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\| *	static cast: support changing size and signedness	Kazuki Sakamoto	2020-06-19	1	-0/+2
* \|	Support missing sub-assign and and-assign operators	Kamil Rakoczy	2020-06-25	1	-0/+2
* \|	Support missing xor-assign operator	Lukasz Dalek	2020-06-24	1	-0/+1
* \|	Add plus-assignment operator	Kamil Rakoczy	2020-06-24	1	-0/+1
* \|	Add or-assignment operator	Kamil Rakoczy	2020-06-24	1	-0/+2
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*	Merge branch 'master' into struct	Peter Crozier	2020-06-03	1	-7/+8
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\| *	Merge pull request #2033 from boqwxp/cleanup-verilog-lexer	whitequark	2020-05-29	1	-6/+5
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\| \| *	verilog: Move lexer location variables from global namespace to `VERILOG_FRON...	Alberto Gonzalez	2020-05-06	1	-6/+5
\| * \|	Silence spurious warning in Verilog lexer when compiling with GCC	Rupert Swarbrick	2020-05-26	1	-1/+3
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* \|	Generalise structs and add support for packed unions.	Peter Crozier	2020-05-12	1	-2/+4
* \|	Implement SV structs.	Peter Crozier	2020-05-08	1	-1/+6
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*	Error duplicate declarations of a typedef name in the same scope.	Peter Crozier	2020-03-24	1	-1/+1
*	Support module/package/interface/block scope for typedef names.	Peter Crozier	2020-03-23	1	-2/+15
*	Parser changes to support typedef.	Peter	2020-03-22	1	-2/+26
*	refixed parsing of constant with comment between size and value	Marcus Comstedt	2020-03-11	1	-8/+23
*	Closes #1717. Add more precise Verilog source location information to AST and...	Alberto Gonzalez	2020-02-23	1	-19/+53
*	verilog: ignore '&&&' when not in -specify mode	Eddie Hung	2020-02-13	1	-1/+1
*	sv: Improve handling of wildcard port connections	David Shah	2020-02-02	1	-1/+1
*	sv: Add lexing and parsing of .* (wildcard port conns)	David Shah	2020-02-02	1	-0/+2
*	Fixed some missing "verilog_" in documentation	Rodrigo Alejandro Melo	2019-12-13	1	-1/+1
*	sv: Correct parsing of always_comb, always_ff and always_latch	David Shah	2019-11-21	1	-3/+3
*	Fix lexing of integer literals without radix	Clifford Wolf	2019-09-13	1	-1/+1
*	Fix lexing of integer literals, fixes #1364	Clifford Wolf	2019-09-12	1	-1/+1
*	verilog_lexer: Increase YY_BUF_SIZE to 65536	David Shah	2019-07-26	1	-0/+3
*	Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi...	Clifford Wolf	2019-07-02	1	-0/+2
*	Fixed brojen $error()/$info/$warning() on non-generate blocks	Udi Finkelstein	2019-06-11	1	-1/+1
*	Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...	Clifford Wolf	2019-06-07	1	-0/+5
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\| *	Initial implementation of elaboration system tasks	Udi Finkelstein	2019-05-03	1	-0/+5
* \|	Merge branch 'master' into wandwor	Stefan Biereigel	2019-05-27	1	-1/+1
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\| * \|	Added support for unsized constants, fixes #1022	Miodrag Milanovic	2019-05-27	1	-1/+1
* \| \|	make lexer/parser aware of wand/wor net types	Stefan Biereigel	2019-05-23	1	-0/+2
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* \|	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify	Clifford Wolf	2019-05-06	1	-0/+2
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\| * \	Merge pull request #988 from YosysHQ/clifford/fix987	Clifford Wolf	2019-05-04	1	-0/+1
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\| \| * \|	Add approximate support for SV "var" keyword, fixes #987	Clifford Wolf	2019-05-04	1	-0/+1
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\| * /	Add support for SVA "final" keyword	Clifford Wolf	2019-05-04	1	-0/+1
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* \|	Improve $specrule interface	Clifford Wolf	2019-04-23	1	-1/+1
* \|	Add $specrule cells for $setup/$hold/$skew specify rules	Clifford Wolf	2019-04-23	1	-0/+11
* \|	Un-break default specify parser	Clifford Wolf	2019-04-23	1	-0/+1
* \|	Add specify parser	Clifford Wolf	2019-04-23	1	-1/+6
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*	Fix handling of cases that look like sva labels, fixes #862	Clifford Wolf	2019-03-10	1	-49/+10
*	Also add support for labels on sva module items, fixes #699	Clifford Wolf	2019-03-08	1	-5/+52
*	Bugfix in Verilog string handling	Clifford Wolf	2019-01-05	1	-1/+1
*	Merge pull request #659 from rubund/sv_interfaces	Clifford Wolf	2018-10-18	1	-0/+8
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\| *	Synthesis support for SystemVerilog interfaces	Ruben Undheim	2018-10-12	1	-0/+8
* \|	ignore protect endprotect	argama	2018-10-16	1	-0/+3
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*	Add "make coverage"	Clifford Wolf	2018-08-27	1	-1/+1
*	Merge pull request #513 from udif/pr_reg_wire_error	Clifford Wolf	2018-08-15	1	-1/+1
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\| *	This PR should be the base for discussion, do not merge it yet!	Udi Finkelstein	2018-03-11	1	-1/+1
* \|	Support more character literals	Dan Gisselquist	2018-05-03	1	-1/+9