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path: root/frontends/verilog/verilog_lexer.l
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* verilog: support for time scale delay valuesZachary Snow2022-02-141-3/+12
* verilog: Squash flex-triggered warning.Marcelina Kościelnicka2021-09-131-0/+2
* verilog: Support tri/triand/trior wire types.Marcelina Kościelnicka2021-08-061-0/+3
* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-161-0/+1
* verilog: Squash a memory leak.Marcelina Kościelnicka2021-06-141-1/+1
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* sv: support remaining assignment operatorsZachary Snow2021-05-251-4/+11
* verilog: revise hot comment warningsZachary Snow2021-03-301-6/+21
* sv: extended support for integer typesZachary Snow2021-02-281-0/+1
* Fix handling of unique/unique0/priority cases in the frontend.Marcelina Kościelnicka2021-02-251-1/+1
* Merge pull request #2179 from splhack/static-castclairexen2020-07-011-0/+2
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| * static cast: support changing size and signednessKazuki Sakamoto2020-06-191-0/+2
* | Support missing sub-assign and and-assign operatorsKamil Rakoczy2020-06-251-0/+2
* | Support missing xor-assign operatorLukasz Dalek2020-06-241-0/+1
* | Add plus-assignment operatorKamil Rakoczy2020-06-241-0/+1
* | Add or-assignment operatorKamil Rakoczy2020-06-241-0/+2
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* Merge branch 'master' into structPeter Crozier2020-06-031-7/+8
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| * Merge pull request #2033 from boqwxp/cleanup-verilog-lexerwhitequark2020-05-291-6/+5
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| | * verilog: Move lexer location variables from global namespace to `VERILOG_FRON...Alberto Gonzalez2020-05-061-6/+5
| * | Silence spurious warning in Verilog lexer when compiling with GCCRupert Swarbrick2020-05-261-1/+3
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* | Generalise structs and add support for packed unions.Peter Crozier2020-05-121-2/+4
* | Implement SV structs.Peter Crozier2020-05-081-1/+6
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* Error duplicate declarations of a typedef name in the same scope.Peter Crozier2020-03-241-1/+1
* Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-231-2/+15
* Parser changes to support typedef.Peter2020-03-221-2/+26
* refixed parsing of constant with comment between size and valueMarcus Comstedt2020-03-111-8/+23
* Closes #1717. Add more precise Verilog source location information to AST and...Alberto Gonzalez2020-02-231-19/+53
* verilog: ignore '&&&' when not in -specify modeEddie Hung2020-02-131-1/+1
* sv: Improve handling of wildcard port connectionsDavid Shah2020-02-021-1/+1
* sv: Add lexing and parsing of .* (wildcard port conns)David Shah2020-02-021-0/+2
* Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-131-1/+1
* sv: Correct parsing of always_comb, always_ff and always_latchDavid Shah2019-11-211-3/+3
* Fix lexing of integer literals without radixClifford Wolf2019-09-131-1/+1
* Fix lexing of integer literals, fixes #1364Clifford Wolf2019-09-121-1/+1
* verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
* Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi...Clifford Wolf2019-07-021-0/+2
* Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-111-1/+1
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...Clifford Wolf2019-06-071-0/+5
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| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-031-0/+5
* | Merge branch 'master' into wandworStefan Biereigel2019-05-271-1/+1
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| * | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-271-1/+1
* | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-231-0/+2
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* | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-061-0/+2
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| * \ Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-041-0/+1
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| | * | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-041-0/+1
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| * / Add support for SVA "final" keywordClifford Wolf2019-05-041-0/+1
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* | Improve $specrule interfaceClifford Wolf2019-04-231-1/+1
* | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+11
* | Un-break default specify parserClifford Wolf2019-04-231-0/+1
* | Add specify parserClifford Wolf2019-04-231-1/+6
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