iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	verilog: Squash a memory leak.	Marcelina Kościelnicka	2021-06-14	1	-8/+4
*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
*	verilog: rebuild user_type_stack from globals before parsing file	Xiretza	2021-03-18	1	-5/+21
*	sv: carry over global typedefs from previous files	Zachary Snow	2021-03-17	1	-2/+5
*	Fix indents.	Tom Verbeure	2021-01-04	1	-2/+2
*	Add -nosynthesis flag for read_verilog command.	Tom Verbeure	2021-01-04	1	-3/+12
*	Fix SYNTHESIS always being defined in Verilog frontend	georgerennie	2020-12-01	1	-0/+3
*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-6/+6
*	frontend: cleanup to use more ID::*, more dict<> instead of map<>	Eddie Hung	2020-05-04	1	-1/+1
*	Merge pull request #1811 from PeterCrozier/typedef_scope	N. Engelhardt	2020-03-30	1	-1/+2
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\| *	Support module/package/interface/block scope for typedef names.	Peter Crozier	2020-03-23	1	-1/+2
* \|	Add support for SystemVerilog-style `define to Verilog frontend	Rupert Swarbrick	2020-03-27	1	-13/+13
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*	Build pkg_user_types before parsing in case of changes in the design.	Peter Crozier	2020-03-22	1	-6/+3
*	Clear pkg_user_types if no packages following a 'design -reset-vlog'.	Peter	2020-03-22	1	-0/+4
*	Parser changes to support typedef.	Peter	2020-03-22	1	-0/+19
*	Closes #1717. Add more precise Verilog source location information to AST and...	Alberto Gonzalez	2020-02-23	1	-1/+1
*	Add "verilog_defines -list" and "verilog_defines -reset"	Clifford Wolf	2019-10-21	1	-0/+16
*	Add "read_verilog -pwires" feature, closes #1106	Clifford Wolf	2019-06-19	1	-1/+9
*	Merge remote-tracking branch 'origin/master' into clifford/specify	Eddie Hung	2019-05-03	1	-2/+2
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\| *	Include filename in "Executing Verilog-2005 frontend" message, fixes #959	Clifford Wolf	2019-04-30	1	-2/+2
* \|	Add specify parser	Clifford Wolf	2019-04-23	1	-5/+13
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*	New behavior for front-end handling of whiteboxes	Clifford Wolf	2019-04-20	1	-9/+20
*	Add "whitebox" attribute, add "read_verilog -wb"	Clifford Wolf	2019-04-18	1	-2/+12
*	Improve read_verilog debug output capabilities	Clifford Wolf	2019-03-21	1	-5/+24
*	Add "read_verilog -noassert -noassume -assert-assumes"	Clifford Wolf	2018-09-24	1	-1/+22
*	Added -no_dump_ptr flag for AST dump options in 'read_verilog'	Udi Finkelstein	2018-08-23	1	-1/+9
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-6/+6
*	Use log_file_warning(), log_file_error() functions.	Henner Zeller	2018-07-20	1	-5/+3
*	Replace -ignore_redef with -[no]overwrite	Clifford Wolf	2018-05-03	1	-6/+17
*	Bugfix in verilog_defaults argument parser	Clifford Wolf	2017-12-24	1	-1/+1
*	Add a paragraph about pre-defined macros to read_verilog help message	Clifford Wolf	2017-07-21	1	-0/+4
*	Added "verilog_defines" command	Clifford Wolf	2016-12-15	1	-0/+60
*	Bugfix in "read_verilog -D NAME=VAL" handling	Clifford Wolf	2016-11-28	1	-3/+3
*	Remember global declarations and defines accross read_verilog calls	Clifford Wolf	2016-11-15	1	-1/+1
*	Added read_verilog -norestrict -assume-asserts	Clifford Wolf	2016-08-26	1	-1/+17
*	Added "read_verilog -dump_rtlil"	Clifford Wolf	2016-07-27	1	-1/+9
*	No tristate warning message for "read_verilog -lib"	Clifford Wolf	2016-07-23	1	-3/+3
*	Small improvements in Verilog front-end docs	Clifford Wolf	2016-05-20	1	-0/+3
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Fixed typos in verilog_defaults help message	Clifford Wolf	2016-03-10	1	-3/+3
*	SystemVerilog also has assume(), added implicit -D FORMAL	Clifford Wolf	2015-10-13	1	-2/+2
*	Added read_verilog -nodpi	Clifford Wolf	2015-09-23	1	-0/+19
*	Re-created command-reference-manual.tex, copied some doc fixes to online help	Clifford Wolf	2015-08-14	1	-6/+6
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-1/+1
*	Add -noautowire option to verilog frontend	Marcus Comstedt	2015-08-01	1	-1/+8
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
*	Verilog front-end: define `BLACKBOX in -lib mode	Clifford Wolf	2015-04-19	1	-1/+2
*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26	1	-1/+11
*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14	1	-1/+15
*	Print "SystemVerilog" in "read_verilog -sv" log messages	Clifford Wolf	2014-10-16	1	-1/+1