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| author | whitequark <whitequark@whitequark.org> | 2020-06-18 23:34:52 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-18 23:34:52 +0000 |
| commit | 7191dd16f9d486fbe107b2c24d1858c8f88329b3 (patch) | |
| tree | 11a32e71b94bc030afc32d3f8d4c8f3d3ada1588 /frontends/verilog/verilog_frontend.cc | |
| parent | dfde1cf1c540d5580d7bc7d24f9f59a004202d60 (diff) | |
| download | yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.tar.gz yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.tar.bz2 yosys-7191dd16f9d486fbe107b2c24d1858c8f88329b3.zip | |
Use C++11 final/override keywords.
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 26abe49b5..2e9c9b2e2 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -67,7 +67,7 @@ static void add_package_types(dict<std::string, AST::AstNode *> &user_types, std struct VerilogFrontend : public Frontend { VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -232,7 +232,7 @@ struct VerilogFrontend : public Frontend { log("supported by the Yosys Verilog front-end.\n"); log("\n"); } - void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override { bool flag_dump_ast1 = false; bool flag_dump_ast2 = false; @@ -503,7 +503,7 @@ struct VerilogFrontend : public Frontend { struct VerilogDefaults : public Pass { VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -524,7 +524,7 @@ struct VerilogDefaults : public Pass { log("not imply -clear.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design*) override { if (args.size() < 2) cmd_error(args, 1, "Missing argument."); @@ -561,7 +561,7 @@ struct VerilogDefaults : public Pass { struct VerilogDefines : public Pass { VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -583,7 +583,7 @@ struct VerilogDefines : public Pass { log(" list currently defined preprocessor symbols\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { |