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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-21 14:34:53 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-21 14:34:53 +0200 |
| commit | 26766da34392aa4dc773c4e0ec36e7a7e59dad3e (patch) | |
| tree | a05bcf915cfeb50de0bdd695157a77603a643781 /frontends/verilog/verilog_frontend.cc | |
| parent | 3a8f6f0f51d527e13f948f18b87a678d35416409 (diff) | |
| download | yosys-26766da34392aa4dc773c4e0ec36e7a7e59dad3e.tar.gz yosys-26766da34392aa4dc773c4e0ec36e7a7e59dad3e.tar.bz2 yosys-26766da34392aa4dc773c4e0ec36e7a7e59dad3e.zip | |
Add a paragraph about pre-defined macros to read_verilog help message
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index fe84c8e80..19fc3c6af 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -168,6 +168,10 @@ struct VerilogFrontend : public Frontend { log("recommended to use a simulator (for example Icarus Verilog) for checking\n"); log("the syntax of the code, rather than to rely on read_verilog for that.\n"); log("\n"); + log("Depending on if read_verilog is run in -formal mode, either the macro\n"); + log("SYNTHESIS or FORMAL is defined automatically. In addition, read_verilog\n"); + log("always defines the macro YOSYS.\n"); + log("\n"); log("See the Yosys README file for a list of non-standard Verilog features\n"); log("supported by the Yosys Verilog front-end.\n"); log("\n"); |