iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #1667 from YosysHQ/clifford/verificnand	Claire Wolf	2020-01-30	1	-0/+8
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\| *	Add Verific support for OPER_REDUCE_NAND	Claire Wolf	2020-01-30	1	-0/+8
* \|	Merge pull request #1503 from YosysHQ/eddie/verific_help	Claire Wolf	2020-01-30	1	-8/+8
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\| * \|	Merge remote-tracking branch 'origin/master' into eddie/verific_help	Eddie Hung	2020-01-27	4	-18/+74
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\| * \|	verific: no help() when no YOSYS_ENABLE_VERIFIC	Eddie Hung	2020-01-27	1	-4/+1
\| * \|	Oops	Eddie Hung	2019-11-19	1	-1/+1
\| * \|	Print help message for verific pass	Eddie Hung	2019-11-19	1	-9/+12
* \| \|	verific: also unflatten for 'hierarchy' flow as per @cliffordwolf	Eddie Hung	2020-01-27	1	-0/+3
* \| \|	verific: unflatten struct ports	Eddie Hung	2020-01-24	1	-0/+3
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* \|	Send people to symbioticeda.com instead of verific.com	Clifford Wolf	2019-12-18	2	-5/+26
* \|	Add Verific support for SVA nexttime properties	Clifford Wolf	2019-11-22	1	-0/+22
* \|	Improve handling of verific primitives in "verific -import -V" mode	Clifford Wolf	2019-11-22	1	-2/+2
* \|	Add Verific SVA support for "always" properties	Clifford Wolf	2019-11-22	1	-5/+15
* \|	Correctly treat empty modules as blackboxes in Verific	Clifford Wolf	2019-11-20	1	-1/+1
* \|	Do not rename VHDL entities to "entity(impl)" when they are top modules	Clifford Wolf	2019-11-20	2	-5/+8
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*	Improve naming scheme for (VHDL) modules imported from Verific	Clifford Wolf	2019-10-24	1	-3/+26
*	Add "verific -L"	Clifford Wolf	2019-10-24	1	-1/+12
*	Fix handling of "restrict" in Verific front-end	Clifford Wolf	2019-10-21	1	-1/+1
*	Fix erroneous ifndef-NDEBUG in verific.cc	Clifford Wolf	2019-08-17	1	-3/+1
*	Fix various NDEBUG compiler warnings, closes #1255	Clifford Wolf	2019-08-13	1	-0/+2
*	Merge pull request #1258 from YosysHQ/eddie/cleanup	Clifford Wolf	2019-08-10	2	-3/+3
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\| *	substr() -> compare()	Eddie Hung	2019-08-07	1	-2/+2
\| *	stoi -> atoi	Eddie Hung	2019-08-07	1	-1/+1
\| *	Use std::stoi instead of atoi(<str>.c_str())	Eddie Hung	2019-08-06	1	-1/+1
\| *	Use State::S{0,1}	Eddie Hung	2019-08-06	1	-1/+1
* \|	Automatically prune init attributes in verific front-end, fixes #1237	Clifford Wolf	2019-08-07	2	-7/+60
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*	Call "read_verilog" with -defer from "read"	Clifford Wolf	2019-07-29	1	-1/+2
*	Only support Symbiotic EDA flavored Verific	Clifford Wolf	2019-06-02	1	-0/+8
*	Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ...	Clifford Wolf	2019-05-30	1	-0/+3
*	For hier_tree::Elaborate() also include SV root modules (bind)	Eddie Hung	2019-05-03	1	-23/+36
*	Fix verific_parameters construction, use attribute to mark top netlists	Eddie Hung	2019-05-03	2	-8/+12
*	WIP -chparam support for hierarchy when verific	Eddie Hung	2019-05-03	2	-12/+17
*	verific_import() changes to avoid ElaborateAll()	Eddie Hung	2019-05-03	1	-15/+38
*	Add "read -verific" and "read -noverific"	Clifford Wolf	2019-03-27	1	-6/+28
*	Fix "verific -extnets" for more complex situations	Clifford Wolf	2019-03-26	1	-15/+71
*	Merge pull request #858 from YosysHQ/clifford/svalabels	Clifford Wolf	2019-03-09	1	-1/+14
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\| *	Add hack for handling SVA labels via Verific	Clifford Wolf	2019-03-07	1	-1/+14
* \|	Update help message for -chparam	Eddie Hung	2019-03-09	1	-1/+2
* \|	Add -chparam option to verific command	Eddie Hung	2019-03-09	1	-2/+18
* \|	Fix spelling	Eddie Hung	2019-03-09	1	-1/+1
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*	Improve "read" error msg	Clifford Wolf	2019-02-28	1	-1/+1
*	Check if Verific was built with DB_PRESERVE_INITIAL_VALUE	Clifford Wolf	2019-02-24	1	-0/+4
*	Remove -m32 Verific eval lib build instructions	Clifford Wolf	2019-01-04	1	-29/+0
*	Improve VerificImporter support for writes to asymmetric memories	Clifford Wolf	2019-01-02	1	-22/+35
*	Fix VerificImporter asymmetric memories error message	Clifford Wolf	2019-01-02	1	-1/+1
*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-4/+4
*	Improve src tagging (using names and attrs) of cells and wires in verific fro...	Clifford Wolf	2018-12-18	2	-99/+160
*	Verific updates	Clifford Wolf	2018-12-06	1	-53/+0
*	Set Verific flag vhdl_support_variable_slice=1	Clifford Wolf	2018-11-09	1	-0/+1
*	Improve Verific importer blackbox handling	Clifford Wolf	2018-10-07	1	-2/+14