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author | Clifford Wolf <clifford@clifford.at> | 2019-10-24 12:13:37 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-10-24 12:13:50 +0200 |
commit | 84982b308343315c889d3d00116db820a51cad78 (patch) | |
tree | 9eabe561c9a24e57bddff83886e996c015bd3e3c /frontends/verific | |
parent | 34dadd9ab20494057c1ac7dae443b48eee0c2c30 (diff) | |
download | yosys-84982b308343315c889d3d00116db820a51cad78.tar.gz yosys-84982b308343315c889d3d00116db820a51cad78.tar.bz2 yosys-84982b308343315c889d3d00116db820a51cad78.zip |
Improve naming scheme for (VHDL) modules imported from Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verific')
-rw-r--r-- | frontends/verific/verific.cc | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index c68390418..a5c4aa26a 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -787,7 +787,18 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates) void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo) { std::string netlist_name = nl->GetAtt(" \\top") ? nl->CellBaseName() : nl->Owner()->Name(); - std::string module_name = nl->IsOperator() ? "$verific$" + netlist_name : RTLIL::escape_id(netlist_name); + std::string module_name = netlist_name; + + if (nl->IsOperator()) { + module_name = "$verific$" + module_name; + } else { + if (*nl->Name()) { + module_name += "("; + module_name += nl->Name(); + module_name += ")"; + } + module_name = "\\" + module_name; + } netlist = nl; @@ -1396,8 +1407,20 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se import_verific_cells: nl_todo.insert(inst->View()); - RTLIL::Cell *cell = module->addCell(inst_name, inst->IsOperator() ? - std::string("$verific$") + inst->View()->Owner()->Name() : RTLIL::escape_id(inst->View()->Owner()->Name())); + std::string inst_type = inst->View()->Owner()->Name(); + + if (inst->View()->IsOperator()) { + inst_type = "$verific$" + inst_type; + } else { + if (*inst->View()->Name()) { + inst_type += "("; + inst_type += inst->View()->Name(); + inst_type += ")"; + } + inst_type = "\\" + inst_type; + } + + RTLIL::Cell *cell = module->addCell(inst_name, inst_type); if (inst->IsPrimitive() && mode_keep) cell->attributes["\\keep"] = 1; |