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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 10:32:18 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 10:32:18 -0800 |
commit | d730bba6d2847515795c32d3a753320b8b48bee0 (patch) | |
tree | a63ec007f9ad45765c51b989644efba36e5f4dac /frontends/verific | |
parent | e2819ce31c20b60b7b5b3a58509006322ceb76ab (diff) | |
download | yosys-d730bba6d2847515795c32d3a753320b8b48bee0.tar.gz yosys-d730bba6d2847515795c32d3a753320b8b48bee0.tar.bz2 yosys-d730bba6d2847515795c32d3a753320b8b48bee0.zip |
verific: no help() when no YOSYS_ENABLE_VERIFIC
Diffstat (limited to 'frontends/verific')
-rw-r--r-- | frontends/verific/verific.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 79730c98a..05c615768 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2073,10 +2073,8 @@ struct VerificPass : public Pass { { static bool set_verific_global_flags = true; - if (check_noverific_env()) { - help(); + if (check_noverific_env()) log_cmd_error("This version of Yosys is built without Verific support.\n"); - } log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n"); @@ -2492,7 +2490,6 @@ struct VerificPass : public Pass { } #else /* YOSYS_ENABLE_VERIFIC */ void execute(std::vector<std::string>, RTLIL::Design *) YS_OVERRIDE { - help(); log_cmd_error("This version of Yosys is built without Verific support.\n"); } #endif |