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| author | Clifford Wolf <clifford@clifford.at> | 2019-11-20 12:54:10 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-11-20 12:54:10 +0100 |
| commit | f6ff311a1dc9876911594328350e2d3fc62a5535 (patch) | |
| tree | a1a5aa06a6c361222c3a880c408b2d31ab691818 /frontends/verific | |
| parent | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (diff) | |
| download | yosys-f6ff311a1dc9876911594328350e2d3fc62a5535.tar.gz yosys-f6ff311a1dc9876911594328350e2d3fc62a5535.tar.bz2 yosys-f6ff311a1dc9876911594328350e2d3fc62a5535.zip | |
Do not rename VHDL entities to "entity(impl)" when they are top modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/verific.cc | 11 | ||||
| -rw-r--r-- | frontends/verific/verific.h | 2 |
2 files changed, 8 insertions, 5 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index a5c4aa26a..c2086afa4 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -784,7 +784,7 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates) merge_past_ffs_clock(it.second, it.first.first, it.first.second); } -void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo) +void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo, bool norename) { std::string netlist_name = nl->GetAtt(" \\top") ? nl->CellBaseName() : nl->Owner()->Name(); std::string module_name = netlist_name; @@ -792,7 +792,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (nl->IsOperator()) { module_name = "$verific$" + module_name; } else { - if (*nl->Name()) { + if (!norename && *nl->Name()) { module_name += "("; module_name += nl->Name(); module_name += ")"; @@ -1899,7 +1899,7 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par Netlist *nl = *nl_todo.begin(); if (nl_done.count(nl) == 0) { VerificImporter importer(false, false, false, false, false, false, false); - importer.import_netlist(design, nl, nl_todo); + importer.import_netlist(design, nl, nl_todo, nl->Owner()->Name() == top); } nl_todo.erase(nl); nl_done.insert(nl); @@ -2373,6 +2373,8 @@ struct VerificPass : public Pass { if (argidx > GetSize(args) && args[argidx].compare(0, 1, "-") == 0) cmd_error(args, argidx, "unknown option"); + std::set<std::string> top_mod_names; + if (mode_all) { log("Running hier_tree::ElaborateAll().\n"); @@ -2401,6 +2403,7 @@ struct VerificPass : public Pass { for (; argidx < GetSize(args); argidx++) { const char *name = args[argidx].c_str(); + top_mod_names.insert(name); VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1); if (veri_lib) { @@ -2466,7 +2469,7 @@ struct VerificPass : public Pass { if (nl_done.count(nl) == 0) { VerificImporter importer(mode_gates, mode_keep, mode_nosva, mode_names, mode_verific, mode_autocover, mode_fullinit); - importer.import_netlist(design, nl, nl_todo); + importer.import_netlist(design, nl, nl_todo, top_mod_names.count(nl->Owner()->Name())); } nl_todo.erase(nl); nl_done.insert(nl); diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 5cbd78f7b..2ccfcd42c 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -93,7 +93,7 @@ struct VerificImporter void merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBit clock, bool clock_pol); void merge_past_ffs(pool<RTLIL::Cell*> &candidates); - void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo); + void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo, bool norename = false); }; void verific_import_sva_assert(VerificImporter *importer, Verific::Instance *inst); |