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* Support asymmetric memories for verific frontendMiodrag Milanovic2020-06-011-6/+1
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* Revert "Add support for non-power-of-two mem chunks in verific importer"Claire Wolf2020-05-171-12/+2
| | | | This reverts commit 173aa27ca5ef6e7c0a9277e8da7765adcd63bfe9.
* Add support for non-power-of-two mem chunks in verific importerClaire Wolf2020-05-141-2/+12
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* verific: ignore anonymous enumsEddie Hung2020-04-301-1/+4
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* verific: support VHDL enums tooEddie Hung2020-04-271-13/+43
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* verific: recover wiretype/enum attr as part of import_attributes()Eddie Hung2020-04-272-6/+35
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* Revert "verific: import enum attributes from verific"Eddie Hung2020-04-241-24/+0
| | | | This reverts commit 5028e17f7db11f901ce9e423dfe2c6f7e68259cc.
* verific: do not assert if wire not found; warn insteadEddie Hung2020-04-231-2/+6
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* verific: import enum attributes from verificEddie Hung2020-04-221-0/+20
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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-48/+48
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* kernel: use more ID::*Eddie Hung2020-04-021-1/+1
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* Merge pull request #1667 from YosysHQ/clifford/verificnandClaire Wolf2020-01-301-0/+8
|\ | | | | Add Verific support for OPER_REDUCE_NAND
| * Add Verific support for OPER_REDUCE_NANDClaire Wolf2020-01-301-0/+8
| | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
* | Merge pull request #1503 from YosysHQ/eddie/verific_helpClaire Wolf2020-01-301-8/+8
|\ \ | | | | | | `verific` pass to print help message when command syntax error
| * | Merge remote-tracking branch 'origin/master' into eddie/verific_helpEddie Hung2020-01-274-18/+74
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| * | verific: no help() when no YOSYS_ENABLE_VERIFICEddie Hung2020-01-271-4/+1
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| * | OopsEddie Hung2019-11-191-1/+1
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| * | Print help message for verific passEddie Hung2019-11-191-9/+12
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* | | verific: also unflatten for 'hierarchy' flow as per @cliffordwolfEddie Hung2020-01-271-0/+3
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* | | verific: unflatten struct portsEddie Hung2020-01-241-0/+3
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* | Send people to symbioticeda.com instead of verific.comClifford Wolf2019-12-182-5/+26
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add Verific support for SVA nexttime propertiesClifford Wolf2019-11-221-0/+22
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve handling of verific primitives in "verific -import -V" modeClifford Wolf2019-11-221-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add Verific SVA support for "always" propertiesClifford Wolf2019-11-221-5/+15
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Correctly treat empty modules as blackboxes in VerificClifford Wolf2019-11-201-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Do not rename VHDL entities to "entity(impl)" when they are top modulesClifford Wolf2019-11-202-5/+8
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve naming scheme for (VHDL) modules imported from VerificClifford Wolf2019-10-241-3/+26
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "verific -L"Clifford Wolf2019-10-241-1/+12
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of "restrict" in Verific front-endClifford Wolf2019-10-211-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix erroneous ifndef-NDEBUG in verific.ccClifford Wolf2019-08-171-3/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix various NDEBUG compiler warnings, closes #1255Clifford Wolf2019-08-131-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1258 from YosysHQ/eddie/cleanupClifford Wolf2019-08-102-3/+3
|\ | | | | Cleanup a few barnacles across codebase
| * substr() -> compare()Eddie Hung2019-08-071-2/+2
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| * stoi -> atoiEddie Hung2019-08-071-1/+1
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| * Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-1/+1
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| * Use State::S{0,1}Eddie Hung2019-08-061-1/+1
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* | Automatically prune init attributes in verific front-end, fixes #1237Clifford Wolf2019-08-072-7/+60
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Call "read_verilog" with -defer from "read"Clifford Wolf2019-07-291-1/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Only support Symbiotic EDA flavored VerificClifford Wolf2019-06-021-0/+8
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ↵Clifford Wolf2019-05-301-0/+3
| | | | | | fixes #1055 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* For hier_tree::Elaborate() also include SV root modules (bind)Eddie Hung2019-05-031-23/+36
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* Fix verific_parameters construction, use attribute to mark top netlistsEddie Hung2019-05-032-8/+12
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* WIP -chparam support for hierarchy when verificEddie Hung2019-05-032-12/+17
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* verific_import() changes to avoid ElaborateAll()Eddie Hung2019-05-031-15/+38
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* Add "read -verific" and "read -noverific"Clifford Wolf2019-03-271-6/+28
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix "verific -extnets" for more complex situationsClifford Wolf2019-03-261-15/+71
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #858 from YosysHQ/clifford/svalabelsClifford Wolf2019-03-091-1/+14
|\ | | | | Add support for using SVA labels in yosys-smtbmc console output
| * Add hack for handling SVA labels via VerificClifford Wolf2019-03-071-1/+14
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Update help message for -chparamEddie Hung2019-03-091-1/+2
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* | Add -chparam option to verific commandEddie Hung2019-03-091-2/+18
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