aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/ast/genrtlil.cc
Commit message (Collapse)AuthorAgeFilesLines
* Encode filename unprintable charsMiodrag Milanovic2022-08-081-8/+8
|
* verilog: fix width/sign detection for functionsZachary Snow2022-05-301-5/+7
|
* verilog: fix size and signedness of array querying functionsJannis Harder2022-05-301-2/+1
| | | | | | | | | | genrtlil.cc and simplify.cc had inconsistent and slightly broken handling of signedness for array querying functions. These functions are defined to return a signed result. Simplify always produced an unsigned and genrtlil always a signed 32-bit result ignoring the context. Includes tests for the the relvant edge cases for context dependent conversions.
* verilog: fix $past's signednessJannis Harder2022-05-251-1/+1
|
* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-141-1/+1
| | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* sv: fix size cast internal expression extensionZachary Snow2022-01-071-2/+9
|
* sv: fix size cast clipping expression widthZachary Snow2022-01-031-1/+2
|
* fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-171-0/+5
| | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* genrtlil: Fix displaying debug info in packagesKamil Rakoczy2021-11-101-1/+2
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-12/+11
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-131-2/+77
| | | | | | | | | | | | | | | | | | | | | | | | | This code now takes the AST nodes of type AST_BIND and generates a representation in the RTLIL for them. This is a little tricky, because a binding of the form: bind baz foo_t foo_i (.arg (1 + bar)); means "make an instance of foo_t called foo_i, instantiate it inside baz and connect the port arg to the result of the expression 1+bar". Of course, 1+bar needs a cell for the addition. Where should that cell live? With this patch, the Binding structure that represents the construct is itself an AST::AstModule module. This lets us put the adder cell inside it. We'll pull the contents out and plonk them into 'baz' when we actually do the binding operation as part of the hierarchy pass. Of course, we don't want RTLIL::Binding to contain an AST::AstModule (since kernel code shouldn't depend on a frontend), so we define RTLIL::Binding as an abstract base class and put the AST-specific code into an AST::Binding subclass. This is analogous to the AST::AstModule class.
* genrtlil: add width detection for AST_PREFIX nodesZachary Snow2021-07-291-0/+8
|
* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-281-3/+6
| | | | Fixes #2447.
* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-161-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This doesn't do anything useful yet: the patch just adds support for the syntax to the lexer and parser and adds some tests to check the syntax parses properly. This generates AST nodes, but doesn't yet generate RTLIL. Since our existing hierarchical_identifier parser doesn't allow bit selects (so you can't do something like foo[1].bar[2].baz), I've also not added support for a trailing bit select (the "constant_bit_select" non-terminal in "bind_target_instance" in the spec). If we turn out to need this in future, we'll want to augment hierarchical_identifier and its other users too. Note that you can't easily use the BNF from the spec: bind_directive ::= "bind" bind_target_scope [ : bind_target_instance_list] bind_instantiation ; | "bind" bind_target_instance bind_instantiation ; even if you fix the lookahead problem, because code like this matches both branches in the BNF: bind a b b_i (.*); The problem is that 'a' could either be a module name or a degenerate hierarchical reference. This seems to be a genuine syntactic ambiguity, which the spec resolves (p739) by saying that we have to wait until resolution time (the hierarchy pass) and take whatever is defined, treating 'a' as an instance name if it names both an instance and a module. To keep the parser simple, it currently accepts this invalid syntax: bind a.b : c d e (.*); This is invalid because we're in the first branch of the BNF above, so the "a.b" term should match bind_target_scope: a module or interface identifier, not an arbitrary hierarchical identifier. This will fail in the hierarchy pass (when it's implemented in a future patch).
* sv: fix two struct access bugsZachary Snow2021-07-151-0/+4
| | | | | - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions)
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-121-3/+1
| | | | | | - add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
* ast: fix error condition causing assert to failXiretza2021-06-141-2/+1
| | | | | type2str returns a string that doesn't start with $ or \, so it can't be assigned to an IdString.
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-091-1/+1
|\ | | | | Fixing old e-mail addresses and deadnames
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-081-2/+9
|/ | | | | | | | The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
* verilog: fix case expression sign and width handlingZachary Snow2021-05-251-10/+40
| | | | | | | | | - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
* verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-081-18/+38
|
* verilog: impose limit on maximum expression widthZachary Snow2021-03-041-0/+6
| | | | | Designs with unreasonably wide expressions would previously get stuck allocating memory forever.
* genrtlil: improve name conflict error messagingZachary Snow2021-02-261-12/+37
|
* frontend: Make helper functions for printing locations.Marcelina Kościelnicka2021-02-231-25/+25
|
* verilog: support recursive functions using ternary expressionsZachary Snow2021-02-121-0/+35
| | | | | | | This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
* genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-051-1/+5
| | | | | | | | This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
* genrtlil: fix mux2rtlil generated wire signednessZachary Snow2020-12-221-0/+1
|
* Sign extend port connections where necessaryZachary Snow2020-12-181-2/+24
| | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
* static cast: support changing size and signednessKazuki Sakamoto2020-06-191-0/+24
| | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* Merge pull request #2041 from PeterCrozier/structclairexen2020-06-041-0/+2
|\ | | | | Implementation of SV structs.
| * Merge branch 'master' into structPeter Crozier2020-06-031-1/+1
| |\
| * | Generalise structs and add support for packed unions.Peter Crozier2020-05-121-0/+1
| | |
| * | Implement SV structs.Peter Crozier2020-05-081-0/+1
| | |
* | | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-041-0/+1
|\ \ \ | |_|/ |/| | Preserve 'signed'-ness of a verilog wire through RTLIL
| * | Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser
* | | Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-191-1/+1
| |/ |/| | | | | Fixes #2058.
* | Merge pull request #2022 from Xiretza/fallthroughswhitequark2020-05-081-3/+4
|\ \ | | | | | | Avoid switch fall-through warnings
| * | Add YS_FALLTHROUGH macro to mark case fall-throughXiretza2020-05-071-3/+4
| | | | | | | | | | | | | | | C++17 introduced [[fallthrough]], GCC and clang had their own vendored attributes before that. MSVC doesn't seem to have such a warning at all.
* | | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-071-4/+19
|\ \ \ | |/ / |/| | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
| * | Fix handling of signed indices in bit slicesClaire Wolf2020-05-021-3/+8
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-021-1/+7
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵Claire Wolf2020-05-021-0/+4
| |/ | | | | | | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-041-1/+1
| |
* | frontend: Include complete source location instead of just ↵Alberto Gonzalez2020-05-011-13/+13
|/ | | | `location.first_line` in `frontends/ast/genrtlil.cc`.
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-211-1/+4
| | | | Fixes #1819, #1820.
* Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-161-3/+128
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Fix 5bba9c3, closes #1876Claire Wolf2020-04-141-7/+13
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-134/+122
|
* kernel: use more ID::*Eddie Hung2020-04-021-45/+45
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-04 09:33:53 +0000