| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | add attributes for enumerated values in ilang | Jeff Wang | 2020-02-17 | 1 | -0/+1 | |
| | | | | | | | - information also useful for strongly-typed enums (not implemented) - resolves enum values in ilang part of #1594 - still need to output enums to VCD (or better yet FST) files | |||||
| * | partial rebase of PeterCrozier's enum work onto current master | Jeff Wang | 2020-01-16 | 1 | -3/+20 | |
| | | | | | | | | | | | | I tried to keep only the enum-related changes, and minimize the diff. (The original commit also had a lot of work done to get typedefs working, but yosys has diverged quite a bit since the 2018-03-09 commit, with a new typedef implementation.) I did not include the import related changes either. Original commit: "Initial implementation of enum, typedef, import. Still a WIP." https://github.com/PeterCrozier/yosys/commit/881833aa738e7404987646ea8076284e911fce3f | |||||
| * | Use "(id)" instead of "id" for types as temporary hack | Clifford Wolf | 2019-10-14 | 1 | -0/+3 | |
| |\ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | sv: Switch parser to glr, prep for typedef | David Shah | 2019-10-03 | 1 | -0/+3 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | Fix for svinterfaces | Eddie Hung | 2019-09-30 | 1 | -2/+8 | |
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| * | | module->derive() to be lazy and not touch ast if already derived | Eddie Hung | 2019-09-30 | 1 | -32/+50 | |
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| * | Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵ | Clifford Wolf | 2019-09-20 | 1 | -18/+29 | |
| | | | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Remove newline | Eddie Hung | 2019-08-29 | 1 | -1/+0 | |
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| * | Restore non-deferred code, deferred case to ignore non constant attr | Eddie Hung | 2019-08-29 | 1 | -5/+12 | |
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| * | read_verilog -defer should still populate module attributes | Eddie Hung | 2019-08-28 | 1 | -5/+6 | |
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| * | handle real values when deriving ast modules | Jakob Wenzel | 2019-08-19 | 1 | -1/+4 | |
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| * | Revert "Merge pull request #1280 from ↵ | Eddie Hung | 2019-08-12 | 1 | -1/+1 | |
| | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f. | |||||
| * | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" | David Shah | 2019-08-10 | 1 | -1/+1 | |
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| * | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 1 | -9/+9 | |
| |\ | | | | | Cleanup a few barnacles across codebase | |||||
| | * | substr() -> compare() | Eddie Hung | 2019-08-07 | 1 | -2/+2 | |
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| | * | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 1 | -7/+7 | |
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| * | | Allow whitebox modules to be overwritten | Eddie Hung | 2019-08-07 | 1 | -1/+1 | |
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| * | initialize noblackbox and nowb in AstModule::clone | Jakob Wenzel | 2019-07-22 | 1 | -0/+2 | |
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| * | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 1 | -2/+6 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵ | Clifford Wolf | 2019-06-07 | 1 | -0/+1 | |
| |\ | | | | | | | clifford/pr983 | |||||
| | * | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 1 | -0/+1 | |
| | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen. | |||||
| * | | Merge branch 'master' into wandwor | Stefan Biereigel | 2019-05-27 | 1 | -1/+16 | |
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| | * | | Added support for unsized constants, fixes #1022 | Miodrag Milanovic | 2019-05-27 | 1 | -1/+16 | |
| | | | | | | | | | | | | | Includes work from @sumit0190 and @AaronKel | |||||
| * | | | remove leftovers from ast data structures | Stefan Biereigel | 2019-05-27 | 1 | -3/+0 | |
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| * | | | fix indentation across files | Stefan Biereigel | 2019-05-23 | 1 | -2/+4 | |
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| * | | | implementation for assignments working | Stefan Biereigel | 2019-05-23 | 1 | -0/+3 | |
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| * | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | Allow $specify[23] cells in blackbox modules | Clifford Wolf | 2019-04-23 | 1 | -0/+6 | |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "noblackbox" attribute | Clifford Wolf | 2019-04-21 | 1 | -17/+27 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | New behavior for front-end handling of whiteboxes | Clifford Wolf | 2019-04-20 | 1 | -16/+68 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -2/+20 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Improve "read_verilog -dump_vlog[12]" handling of upto ranges | Clifford Wolf | 2019-03-21 | 1 | -3/+6 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Improve read_verilog debug output capabilities | Clifford Wolf | 2019-03-21 | 1 | -9/+17 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -2/+2 | |
| | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | |||||
| * | Various indenting fixes in AST front-end (mostly space vs tab issues) | Clifford Wolf | 2018-11-04 | 1 | -6/+3 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Refactor code to avoid code duplication + added comments | Ruben Undheim | 2018-10-20 | 1 | -113/+99 | |
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| * | Support for SystemVerilog interfaces as a port in the top level module + ↵ | Ruben Undheim | 2018-10-20 | 1 | -3/+105 | |
| | | | | | test case | |||||
| * | Fixed memory leak | Ruben Undheim | 2018-10-20 | 1 | -0/+1 | |
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| * | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 1 | -3/+28 | |
| | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport) | |||||
| * | Fix build error with clang | Ruben Undheim | 2018-10-12 | 1 | -1/+1 | |
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| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -4/+36 | |
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| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -11/+122 | |
| | | | | | This time doing the changes mostly in AST before RTLIL generation | |||||
| * | Added -no_dump_ptr flag for AST dump options in 'read_verilog' | Udi Finkelstein | 2018-08-23 | 1 | -6/+9 | |
| | | | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same. | |||||
| * | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 1 | -1/+7 | |
| |\ | | | | | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test) | |||||
| | * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -0/+1 | |
| | | | | | | | | | No longer false warnings for memories and assertions | |||||
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -1/+6 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) | |||||
| * | | Convert more log_error() to log_file_error() where possible. | Henner Zeller | 2018-07-20 | 1 | -7/+6 | |
| | | | | | | | | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion. | |||||
| * | | Replace -ignore_redef with -[no]overwrite | Clifford Wolf | 2018-05-03 | 1 | -5/+13 | |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Turned a few member functions into const, esp. dumpAst(), dumpVlog(). | Udi Finkelstein | 2017-09-30 | 1 | -7/+7 | |
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index : iCE40/yosys | |
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