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* verilog: Fix const eval of unbased unsized constantsJannis Harder2023-04-201-1/+1
| | | | | | | | | | | | | | When the verilog frontend perfomed constant evaluation of unbased unsized constants in a context-determined expression it did not properly extend them by repeating the bit value. This only affected constant evaluation and not constants that made it through unchanged to RTLIL. The latter case was already covered by tests and working before. This fixes the const-eval issue by checking the `is_unsized` flag in bitsAsConst and extending the value accordingly. The newly added test also tests the already working non-const-eval case to highlight that both cases should behave the same.
* Index struct/union members within corresponding wire chunksDag Lem2023-03-051-1/+7
| | | | | This guards against access to bits outside of struct/union members via dynamic indexing.
* Fixes for some of clang scan-build detected issuesMiodrag Milanovic2023-01-171-1/+2
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* fix dumpAst() compilation warningZachary Snow2022-01-181-1/+1
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* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-14/+55
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-251-23/+44
| | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-131-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | This code now takes the AST nodes of type AST_BIND and generates a representation in the RTLIL for them. This is a little tricky, because a binding of the form: bind baz foo_t foo_i (.arg (1 + bar)); means "make an instance of foo_t called foo_i, instantiate it inside baz and connect the port arg to the result of the expression 1+bar". Of course, 1+bar needs a cell for the addition. Where should that cell live? With this patch, the Binding structure that represents the construct is itself an AST::AstModule module. This lets us put the adder cell inside it. We'll pull the contents out and plonk them into 'baz' when we actually do the binding operation as part of the hierarchy pass. Of course, we don't want RTLIL::Binding to contain an AST::AstModule (since kernel code shouldn't depend on a frontend), so we define RTLIL::Binding as an abstract base class and put the AST-specific code into an AST::Binding subclass. This is analogous to the AST::AstModule class.
* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-281-1/+3
| | | | Fixes #2447.
* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This doesn't do anything useful yet: the patch just adds support for the syntax to the lexer and parser and adds some tests to check the syntax parses properly. This generates AST nodes, but doesn't yet generate RTLIL. Since our existing hierarchical_identifier parser doesn't allow bit selects (so you can't do something like foo[1].bar[2].baz), I've also not added support for a trailing bit select (the "constant_bit_select" non-terminal in "bind_target_instance" in the spec). If we turn out to need this in future, we'll want to augment hierarchical_identifier and its other users too. Note that you can't easily use the BNF from the spec: bind_directive ::= "bind" bind_target_scope [ : bind_target_instance_list] bind_instantiation ; | "bind" bind_target_instance bind_instantiation ; even if you fix the lookahead problem, because code like this matches both branches in the BNF: bind a b b_i (.*); The problem is that 'a' could either be a module name or a degenerate hierarchical reference. This seems to be a genuine syntactic ambiguity, which the spec resolves (p739) by saying that we have to wait until resolution time (the hierarchy pass) and take whatever is defined, treating 'a' as an instance name if it names both an instance and a module. To keep the parser simple, it currently accepts this invalid syntax: bind a.b : c d e (.*); This is invalid because we're in the first branch of the BNF above, so the "a.b" term should match bind_target_scope: a module or interface identifier, not an arbitrary hierarchical identifier. This will fail in the hierarchy pass (when it's implemented in a future patch).
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* sv: support tasks and functions within packagesZachary Snow2021-06-011-0/+20
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* Change the type of current_module to ModuleRupert Swarbrick2021-05-131-23/+25
| | | | | | | | | | | The current_module global is needed so that genRTLIL has somewhere to put cells and wires that it generates as it makes sense of expressions that it sees. However, that doesn't actually need to be an AstModule: the Module base class is enough. This patch should cause no functional change, but the point is that it's now possible to call genRTLIL with a module that isn't an AstModule as "current_module". This will be needed for 'bind' support.
* Use range-based for loop in AST::processRupert Swarbrick2021-05-131-21/+21
| | | | | | No functional change: just get rid of the explicit iterator and replace (*it)-> with child->. It's even the same number of characters, but is hopefully a little easier to read.
* ast: make design available to process_module()Zachary Snow2021-03-241-8/+8
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* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-2/+25
| | | | | | | | | | | | Calling log_signal is problematic for several reasons: - with recent changes, empty string is serialized as { }, which violates the "no spaces in IdString" rule - the type (plain / real / signed / string) is dropped, wrongly conflating functionally different values and potentially introducing a subtle elaboration bug Instead, use a custom simple serialization scheme.
* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-121-1/+0
| | | | | | This defers the simplification of globals so that globals in one file may depend on globals in other files. Adds a simplify() call downstream because globals are appended at the end.
* verilog: disallow overriding global parametersZachary Snow2021-03-111-0/+2
| | | | | | It was previously possible to override global parameters on a per-instance basis. This could be dangerous when using positional parameter bindings, hiding oversupplied parameters.
* Merge pull request #2643 from zachjs/fix-param-no-default-logwhitequark2021-03-081-1/+1
|\ | | | | Fix param without default log line
| * Fix param without default log lineZachary Snow2021-03-071-1/+1
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* | verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-081-0/+2
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* Merge pull request #2626 from zachjs/param-no-defaultwhitequark2021-03-071-2/+27
|\ | | | | sv: support for parameters without default values
| * sv: support for parameters without default valuesZachary Snow2021-03-021-2/+27
| | | | | | | | | | | | | | | | | | - Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
* | sv: fix some edge cases for unbased unsized literalsZachary Snow2021-03-061-0/+2
|/ | | | | | - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst`
* frontend: Make helper functions for printing locations.Marcelina Kościelnicka2021-02-231-8/+16
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* ast: fix dump_vlog display of casex/casezMarcelina Kościelnicka2021-01-291-2/+2
| | | | | | The first child of AST_CASE is the case expression, it's subsequent childrean that are AST_COND* and can be used to discriminate the type of the case.
* Return correct modname when found in cache.Julius Roob2020-11-261-0/+1
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* Added $high(), $low(), $left(), $right()Udi Finkelstein2020-09-151-0/+6
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* static cast: support changing size and signednessKazuki Sakamoto2020-06-191-0/+1
| | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* Generalise structs and add support for packed unions.Peter Crozier2020-05-121-0/+1
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* Implement SV structs.Peter Crozier2020-05-081-0/+2
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* Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-021-0/+2
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed ↵Claire Wolf2020-05-021-0/+4
| | | | | | offset, fixes #1990 Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Clear current_scope when done with RTLIL generation, fixes #1837Claire Wolf2020-04-221-0/+4
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-211-2/+0
| | | | Fixes #1819, #1820.
* Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-211-0/+5
|\ | | | | Improved rewrite code for writing to bit slice
| * Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-161-0/+5
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | ast, rpc: record original name of $paramod\* as \hdlname attribute.whitequark2020-04-181-0/+3
| | | | | | | | | | | | | | | | | | | | The $paramod name mangling is not invertible (the \ character, which separates the module name from the parameters, is valid in the module name itself), which does not stop people from trying to invert it. This commit makes it easy to invert the name mangling by storing the original name explicitly, and fixes the firrtl backend to use the newly introduced attribute.
* | ast: Fix handling of identifiers in the global scopeDavid Shah2020-04-161-0/+2
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-34/+34
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* kernel: use more ID::*Eddie Hung2020-04-021-6/+6
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* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-021-33/+39
|\ | | | | kernel: speedup by using more pass-by-const-ref
| * kernel: more pass by const ref, more speedupsEddie Hung2020-03-181-33/+39
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* | Merge pull request #1783 from boqwxp/astcc_cleanupEddie Hung2020-03-301-13/+20
|\ \ | | | | | | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
| * | Add explanatory comment about inefficient wire removal and remove ↵Alberto Gonzalez2020-03-301-4/+8
| | | | | | | | | | | | | | | | | | superfluous call to `fixup_ports()`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | Revert over-aggressive change to a more modest cleanup.Alberto Gonzalez2020-03-271-2/+3
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| * | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.Alberto Gonzalez2020-03-191-11/+13
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* / Simplify was not being called for packages. Broke typedef enums.Peter Crozier2020-03-221-5/+8
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* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-32/+14
|\ | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-32/+14
| | | | | | | | and RTLIL nodes.
* | ast: quiet down when deriving blackbox modulesEddie Hung2020-02-271-11/+19
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