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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-20 11:57:39 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-20 11:57:39 +0200 |
| commit | d9a438101298710b9dadd4e7a1cb0041e8ba4199 (patch) | |
| tree | 9352b2fc99364b028fd899e41961217ab9c493ee /frontends/ast/ast.cc | |
| parent | 11c8a9eb960fdb0a412fabcfbe787cbf5cc3a67d (diff) | |
| download | yosys-d9a438101298710b9dadd4e7a1cb0041e8ba4199.tar.gz yosys-d9a438101298710b9dadd4e7a1cb0041e8ba4199.tar.bz2 yosys-d9a438101298710b9dadd4e7a1cb0041e8ba4199.zip | |
Fixed memory leak
Diffstat (limited to 'frontends/ast/ast.cc')
| -rw-r--r-- | frontends/ast/ast.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 7600e2912..1f2ecffde 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1120,6 +1120,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT // Generate RTLIL from AST for the new module and add to the design: AstModule *newmod = process_module(new_ast, false); + delete(new_ast); design->add(newmod); RTLIL::Module* mod = design->module(original_name); if (is_top) |