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| author | Jeff Wang <jjj11x@gmail.com> | 2020-02-03 01:12:24 -0500 |
|---|---|---|
| committer | Jeff Wang <jeff.wang@utexas.edu> | 2020-02-17 04:42:42 -0500 |
| commit | d12ba42a741464d410773471813d0a78a7ae1db2 (patch) | |
| tree | 218359053ff4c633932531a279cc8635244b88ec /frontends/ast/ast.cc | |
| parent | 6320f2692bc97d9d447622c1ba55a90cfe9dd411 (diff) | |
| download | yosys-d12ba42a741464d410773471813d0a78a7ae1db2.tar.gz yosys-d12ba42a741464d410773471813d0a78a7ae1db2.tar.bz2 yosys-d12ba42a741464d410773471813d0a78a7ae1db2.zip | |
add attributes for enumerated values in ilang
- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
Diffstat (limited to 'frontends/ast/ast.cc')
| -rw-r--r-- | frontends/ast/ast.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 135750837..239813810 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1222,6 +1222,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump } else { // must be global definition + (*it)->simplify(false, false, false, 1, -1, false, false); //process enum/other declarations design->verilog_globals.push_back((*it)->clone()); } } |