Synthesis support for SystemVerilog interfaces

This time doing the changes mostly in AST before RTLIL generation

1 files changed, 122 insertions, 11 deletions

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index e79be953a..256c08776 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -905,7 +905,7 @@ RTLIL::Const AstNode::realAsConst(int width)
 // create a new AstModule from an AST_MODULE AST node
 static AstModule* process_module(AstNode *ast, bool defer)
 {
-	log_assert(ast->type == AST_MODULE);
+	log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE);
 
 	if (defer)
 		log("Storing AST representation for module `%s'.\n", ast->str.c_str());
@@ -916,6 +916,7 @@ static AstModule* process_module(AstNode *ast, bool defer)
 	current_module->ast = NULL;
 	current_module->name = ast->str;
 	current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
+	current_module->set_bool_attribute("\\cells_not_processed");
 
 	current_ast_mod = ast;
 	AstNode *ast_before_simplify = ast->clone();
@@ -989,6 +990,8 @@ static AstModule* process_module(AstNode *ast, bool defer)
 		ignoreThisSignalsInInitial = RTLIL::SigSpec();
 	}
 
+	if (ast->type == AST_INTERFACE)
+		current_module->set_bool_attribute("\\is_interface");
 	current_module->ast = ast_before_simplify;
 	current_module->nolatches = flag_nolatches;
 	current_module->nomeminit = flag_nomeminit;
@@ -1031,7 +1034,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 	log_assert(current_ast->type == AST_DESIGN);
 	for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++)
 	{
-		if ((*it)->type == AST_MODULE)
+		if ((*it)->type == AST_MODULE || (*it)->type == AST_INTERFACE)
 		{
 			for (auto n : design->verilog_globals)
 				(*it)->children.push_back(n->clone());
@@ -1083,8 +1086,123 @@ AstModule::~AstModule()
 		delete ast;
 }
 
+void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module*> local_interfaces)
+{
+	bool is_top = false;
+	AstNode *new_ast = ast->clone();
+	for (auto &intf : local_interfaces) {
+		std::string intfname = intf.first.str();
+		RTLIL::Module *intfmodule = intf.second;
+		for (auto &wire_it : intfmodule->wires_){
+			AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true)));
+			std::string newname = log_id(wire_it.first);
+			newname = intfname + "." + newname;
+			wire->str = newname;
+			new_ast->children.push_back(wire);
+		}
+	}
+	std::string original_name = this->name.str();
+	std::string changed_name = original_name + "_before_replacing_local_interfaces";
+	design->rename(this, changed_name);
+	this->set_bool_attribute("\\to_delete");
+	if (this->get_bool_attribute("\\initial_top")) {
+		this->attributes.erase("\\initial_top");
+		is_top = true;
+	}
+	AstModule *newmod = process_module(new_ast, false);
+	design->add(newmod);
+	RTLIL::Module* mod = design->module(original_name);
+	if (is_top)
+		mod->set_bool_attribute("\\top");
+	mod->set_bool_attribute("\\interfaces_replaced_in_module");
+}
+
+// create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
+RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, bool mayfail)
+{
+	AstNode *new_ast = NULL;
+	std::string modname = derive_common(design, parameters, &new_ast, mayfail);
+
+	// Since interfaces themselves may be instantiated with different parameters,
+	// "modname" must also take those into account, so that unique modules
+	// are derived for any variant of interface connections:
+	std::string interf_info = "";
+
+	bool has_interfaces = false;
+	for(auto &intf : interfaces) {
+		interf_info += log_id(intf.second->name);
+		has_interfaces = true;
+	}
+
+	if (has_interfaces)
+		modname += "$interfaces$" + interf_info;
+
+
+	if (!design->has(modname)) {
+		new_ast->str = modname;
+		for(auto &intf : interfaces) {
+			RTLIL::Module * intfmodule = intf.second;
+			std::string intfname = intf.first.str();
+			for (auto &wire_it : intfmodule->wires_){
+				AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true)));
+				std::string origname = log_id(wire_it.first);
+				std::string newname = intfname + "." + origname;
+				wire->str = newname;
+				wire->is_input = true;
+				wire->is_output = true;
+				new_ast->children.push_back(wire);
+			}
+		}
+
+		design->add(process_module(new_ast, false));
+		design->module(modname)->check();
+
+		RTLIL::Module* mod = design->module(modname);
+
+		for(auto &intf : interfaces) {
+			if(mod->wires_.count(intf.first)) {
+				mod->wires_.erase(intf.first);
+				mod->fixup_ports();
+				RTLIL::Cell * new_subcell = mod->addCell(intf.first, intf.second->name);
+				new_subcell->set_bool_attribute("\\is_interface");
+			}
+			else {
+				log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname);
+			}
+		}
+
+		if (interfaces.size() > 0) {
+			mod->set_bool_attribute("\\interfaces_replaced_in_module");
+		}
+
+	} else {
+		log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
+	}
+
+	delete new_ast;
+	return modname;
+}
+
+// create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
+RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail)
+{
+	AstNode *new_ast = NULL;
+	std::string modname = derive_common(design, parameters, &new_ast, mayfail);
+
+	if (!design->has(modname)) {
+		new_ast->str = modname;
+		design->add(process_module(new_ast, false));
+		design->module(modname)->check();
+	} else {
+		log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
+	}
+
+	delete new_ast;
+	return modname;
+}
+
 // create a new parametric module (when needed) and return the name of the generated module
-RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool)
+std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool)
 {
 	std::string stripped_name = name.str();
 
@@ -1156,15 +1274,8 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 	else
 		modname = "$paramod" + stripped_name + para_info;
 
-	if (!design->has(modname)) {
-		new_ast->str = modname;
-		design->add(process_module(new_ast, false));
-		design->module(modname)->check();
-	} else {
-		log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
-	}
 
-	delete new_ast;
+	(*new_ast_out) = new_ast;
 	return modname;
 }