| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | write_xaiger: inherit port ordering from original module | Eddie Hung | 2019-12-27 | 1 | -5/+16 |
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| * | Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup" | Eddie Hung | 2019-12-27 | 1 | -19/+27 |
| | | | | | | This reverts commit 92654f73ea92ee9e390c8ab50d8cb51c47a7ffa9, reversing changes made to 3e14ff16676884a1f65cf0eeb0ca9cb1958b8804. | ||||
| * | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-12-27 | 1 | -27/+19 |
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| | * | Revert "write_xaiger: only instantiate each whitebox cell type once" | David Shah | 2019-12-27 | 1 | -27/+19 |
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| * | | write_xaiger: simplify c{i,o}_bits | Eddie Hung | 2019-12-27 | 1 | -12/+6 |
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| * | write_xaiger: only instantiate each whitebox cell type once | Eddie Hung | 2019-12-20 | 1 | -19/+27 |
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| * | Revert "Optimise write_xaiger" | Eddie Hung | 2019-12-20 | 1 | -24/+21 |
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| * | Stray newline | Eddie Hung | 2019-12-06 | 1 | -1/+0 |
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| * | write_xaiger to inst each cell type once, do not call techmap/aigmap | Eddie Hung | 2019-12-06 | 1 | -21/+25 |
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| * | Revert "Fold loop" | Eddie Hung | 2019-11-27 | 1 | -3/+6 |
| | | | | | This reverts commit a30d5e1cc35791a98b2269c5e587c566fe8b0a35. | ||||
| * | latch -> box | Eddie Hung | 2019-11-26 | 1 | -1/+1 |
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| * | Fold loop | Eddie Hung | 2019-11-26 | 1 | -6/+3 |
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| * | Do not sigmap keep bits inside write_xaiger | Eddie Hung | 2019-11-26 | 1 | -1/+1 |
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| * | xaiger: do not promote output wires | Eddie Hung | 2019-11-26 | 1 | -5/+0 |
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| * | write_verilog: add -extmem option, to write split memory init files. | whitequark | 2019-11-18 | 1 | -10/+80 |
| | | | | | | Some toolchains (in particular Quartus) are pathologically slow if a large amount of assignments in `initial` blocks are used. | ||||
| * | Use cell name for btor bad state props when it is a public name | Clifford Wolf | 2019-11-14 | 1 | -9/+5 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add an info string symbol for bad states in btor backend | Makai Mann | 2019-11-11 | 1 | -1/+10 |
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| * | Fix write_aiger bug added in 524af21 | Clifford Wolf | 2019-11-04 | 1 | -0/+3 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge pull request #1393 from whitequark/write_verilog-avoid-init | Clifford Wolf | 2019-10-27 | 1 | -4/+5 |
| |\ | | | | | write_verilog: do not print (*init*) attributes on regs | ||||
| | * | write_verilog: do not print (*init*) attributes on regs. | whitequark | 2019-09-22 | 1 | -4/+5 |
| | | | | | | | | | | | | | | | | | | | | | If an init value is emitted for a reg, an (*init*) attribute is never necessary, since it is exactly equivalent. On the other hand, some tools that consume Verilog (ISE, Vivado, Quartus) complain about (*init*) attributes because their interpretation differs from Yosys. All (*init*) attributes that would not become reg init values anyway are emitted as before. | ||||
| * | | Bugfix in smtio vcd handling of $-identifiers | Clifford Wolf | 2019-10-23 | 1 | -6/+9 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -9/+9 |
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| * | | Change smtbmc "Warmup failed" status to "PREUNSAT" | Clifford Wolf | 2019-10-03 | 1 | -14/+14 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Fix btor back-end to use "state" instead of "input" for undef init bits | Clifford Wolf | 2019-10-02 | 1 | -6/+9 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 1 | -8/+8 |
| |\ \ | | | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5) | ||||
| | * | | "abc_padding" attr for blackbox outputs that were padded, remove them later | Eddie Hung | 2019-09-23 | 1 | -1/+6 |
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| | * | | Force $inout.out ports to begin with '$' to indicate internal | Eddie Hung | 2019-09-23 | 1 | -1/+1 |
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| | * | | When two boxes connect to each other, need not be a (* keep *) | Eddie Hung | 2019-09-19 | 1 | -6/+1 |
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| * | | | Merge pull request #1413 from YosysHQ/mmicko/backend_binary_out | Miodrag Milanović | 2019-09-29 | 3 | -4/+4 |
| |\ \ \ | | | | | | | | | Support binary files for backends, fixes #1407 | ||||
| | * | | | Add aiger and protobuf backends binary support | Miodrag Milanovic | 2019-09-28 | 2 | -3/+3 |
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| | * | | | Support binary files for backends, fixes #1407 | Miodrag Milanovic | 2019-09-28 | 1 | -1/+1 |
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| * / / | Corrects btor2 backend | Aman Goel | 2019-09-27 | 1 | -1/+4 |
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| * | | Add "write_aiger -L" | Clifford Wolf | 2019-09-18 | 1 | -5/+16 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Fix stupid bug in btor back-end | Clifford Wolf | 2019-09-18 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | backends: smt2: use $(CXX) variable for compiler | Sean Cross | 2019-09-08 | 1 | -1/+1 |
| |/ | | | | | | | | | | | The Makefile assumes the compiler is called `gcc`, which isn't always true. In fact, if we're building on msys2 or msys2-64, the compiler is called `i686-w64-mingw32-g++` or `x86_64-w64-mingw32-g++`. Use the variable instead of hardcoding the name, to fix building on these systems. Signed-off-by: Sean Cross <sean@xobs.io> | ||||
| * | Recognise built-in types (e.g. $_DFF_*) | Eddie Hung | 2019-08-30 | 1 | -3/+3 |
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| * | Revert "Revert "Fix omode which inserts an output if none exists (otherwise ↵ | Eddie Hung | 2019-08-28 | 1 | -7/+8 |
| | | | | | | | abc9 breaks)"" This reverts commit 8f0c1232d7c511a6473f4581e4c27a90088cedb7. | ||||
| * | Revert "Output "h" extension only if boxes" | Eddie Hung | 2019-08-28 | 1 | -32/+28 |
| | | | | | This reverts commit 399ac760ff2bf4a7d438ed388820e7bfb511de6b. | ||||
| * | Output "h" extension only if boxes | Eddie Hung | 2019-08-21 | 1 | -28/+32 |
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| * | Revert "Fix omode which inserts an output if none exists (otherwise abc9 ↵ | Eddie Hung | 2019-08-21 | 1 | -8/+7 |
| | | | | | | | breaks)" This reverts commit 8182cb9d91555d5be52abbfeeb5d22af05342d8a. | ||||
| * | Fix omode which inserts an output if none exists (otherwise abc9 breaks) | Eddie Hung | 2019-08-20 | 1 | -7/+8 |
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| * | Revert "Only xaig if GetSize(output_bits) > 0" | Eddie Hung | 2019-08-20 | 1 | -149/+147 |
| | | | | | This reverts commit 7b646101e936cacd20938c20ddfbaa63ee268fb2. | ||||
| * | Only xaig if GetSize(output_bits) > 0 | Eddie Hung | 2019-08-20 | 1 | -147/+149 |
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| * | Remove sequential extension | Eddie Hung | 2019-08-20 | 1 | -270/+29 |
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| * | Do not sigmap! | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
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| * | Minor refactor | Eddie Hung | 2019-08-20 | 1 | -7/+6 |
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| * | Output i/o/h extensions even if no boxes or flops | Eddie Hung | 2019-08-19 | 1 | -65/+66 |
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| * | Add (* abc_arrival *) attribute | Eddie Hung | 2019-08-19 | 1 | -9/+66 |
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| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-19 | 1 | -1/+1 |
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| | * | Fix various NDEBUG compiler warnings, closes #1255 | Clifford Wolf | 2019-08-13 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
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index : iCE40/yosys | |
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