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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 21:58:04 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 21:58:04 -0700 |
| commit | c340fbfab23c582103402bbd812d9bca4510dc41 (patch) | |
| tree | 6aef6aa91610b8247b97ad9eb7fc0308bc294915 /backends | |
| parent | 11ac37733d436d5c0217fa6da029d620ec3da1b3 (diff) | |
| download | yosys-c340fbfab23c582103402bbd812d9bca4510dc41.tar.gz yosys-c340fbfab23c582103402bbd812d9bca4510dc41.tar.bz2 yosys-c340fbfab23c582103402bbd812d9bca4510dc41.zip | |
Force $inout.out ports to begin with '$' to indicate internal
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index cbce4c83b..21b281708 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -424,7 +424,7 @@ struct XAigerWriter // inherit existing inout's drivers if ((wire->port_input && wire->port_output && !undriven_bits.count(bit)) || keep_bits.count(bit)) { - RTLIL::IdString wire_name = wire->name.str() + "$inout.out"; + RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str()); RTLIL::Wire *new_wire = module->wire(wire_name); if (!new_wire) new_wire = module->addWire(wire_name, GetSize(wire)); |