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Author
Age
Files
Lines
*
Remove sequential extension
Eddie Hung
2019-08-20
1
-270
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+29
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Do not sigmap!
Eddie Hung
2019-08-20
1
-2
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+2
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Minor refactor
Eddie Hung
2019-08-20
1
-7
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+6
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Output i/o/h extensions even if no boxes or flops
Eddie Hung
2019-08-19
1
-65
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+66
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Add (* abc_arrival *) attribute
Eddie Hung
2019-08-19
1
-9
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+66
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-08-19
1
-1
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+1
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Fix various NDEBUG compiler warnings, closes #1255
Clifford Wolf
2019-08-13
1
-1
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+1
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Use %d
Eddie Hung
2019-08-19
1
-1
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+1
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Merge branch 'eddie/abc9_refactor' into xaig_dff
Eddie Hung
2019-08-16
12
-209
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+353
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Compute abc_scc_break and move CI/CO outside of each abc9
Eddie Hung
2019-08-16
1
-42
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+0
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Merge pull request #1258 from YosysHQ/eddie/cleanup
Clifford Wolf
2019-08-10
9
-33
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+33
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substr() -> compare()
Eddie Hung
2019-08-07
5
-6
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+6
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RTLIL::S{0,1} -> State::S{0,1}
Eddie Hung
2019-08-07
4
-12
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+12
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Merge remote-tracking branch 'origin/master' into eddie/cleanup
Eddie Hung
2019-08-07
2
-106
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+240
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Use IdString::begins_with()
Eddie Hung
2019-08-06
1
-2
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+2
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RTLIL::S{0,1} -> State::S{0,1}
Eddie Hung
2019-08-06
1
-5
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+5
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Use State::S{0,1}
Eddie Hung
2019-08-06
3
-6
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+6
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Make liberal use of IdString.in()
Eddie Hung
2019-08-06
2
-2
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+2
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Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell
Clifford Wolf
2019-08-10
1
-1
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+1
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Merge branch 'master' into firrtl_err_on_unsupported_cell
Jim Lawson
2019-08-07
9
-116
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+287
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Call log_error() instead of log_warning() on unsupported cell type in FIRRTL ...
Jim Lawson
2019-07-24
1
-1
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+1
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Run "clean -purge" on holes_module in its own design
Eddie Hung
2019-08-07
1
-6
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+11
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Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
Clifford Wolf
2019-08-07
1
-93
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+203
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Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog...
Jim Lawson
2019-07-31
1
-93
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+203
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Merge pull request #1241 from YosysHQ/clifford/jsonfix
David Shah
2019-08-07
1
-13
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+37
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Implement improved JSON attr/param encoding
Clifford Wolf
2019-08-01
1
-13
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+37
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Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
Clifford Wolf
2019-08-06
6
-3
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+40
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Merge pull request #1238 from mmicko/vsbuild_fix
Clifford Wolf
2019-08-02
1
-1
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+1
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Visual Studio build fix
Miodrag Milanovic
2019-07-31
1
-1
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+1
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Fix formatting for msys2 mingw build using GetSize
Miodrag Milanovic
2019-08-01
1
-6
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+6
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Merge pull request #1203 from whitequark/write_verilog-zero-width-values
Clifford Wolf
2019-07-18
1
-1
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+2
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write_verilog: dump zero width constants correctly.
whitequark
2019-07-16
1
-1
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+2
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Remove old $pmux_safe code from write_verilog
Clifford Wolf
2019-07-17
1
-5
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+4
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smt: handle failure of setrlimit syscall
N. Engelhardt
2019-07-15
1
-1
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+5
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Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark
Clifford Wolf
2019-07-11
1
-2
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+8
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write_verilog: write RTLIL::Sa aka - as Verilog ?.
whitequark
2019-07-09
1
-2
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+8
*
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abc_flop to also get topologically sorted
Eddie Hung
2019-07-10
1
-11
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+10
*
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Fix clk_pol for FD*_1
Eddie Hung
2019-07-10
1
-1
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+0
*
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Fix spacing
Eddie Hung
2019-07-10
1
-1
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+1
*
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Change how to specify flops to ABC again
Eddie Hung
2019-07-10
1
-10
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+20
*
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Use split_tokens()
Eddie Hung
2019-07-10
1
-17
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+11
*
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-07-10
3
-15
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+34
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Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
Clifford Wolf
2019-07-09
1
-3
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+2
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write_verilog: fix placement of case attributes. NFC.
whitequark
2019-07-09
1
-3
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+2
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Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore
Eddie Hung
2019-07-09
1
-4
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+6
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Rename __builtin_bswap32 -> bswap32
Eddie Hung
2019-07-09
1
-4
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+6
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verilog_backend: dump attributes on SwitchRule.
whitequark
2019-07-08
1
-0
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+1
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verilog_backend: dump attributes on CaseRule, as comments.
whitequark
2019-07-08
1
-6
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+10
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Allow attributes on individual switch cases in RTLIL.
whitequark
2019-07-08
1
-0
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+5
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write_xaiger to treat unknown cell connections as keep-s
Eddie Hung
2019-07-02
1
-6
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+14
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