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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 12:20:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 12:20:08 -0700 |
| commit | 6d77236f3845cd8785e7bdd4da3c5ef966be6043 (patch) | |
| tree | 9a55ec79ecd07e4077dbb90634be19e168b15e48 /backends | |
| parent | 71eff6f0deae3ffaf75cca22768b66a2dc918b3e (diff) | |
| download | yosys-6d77236f3845cd8785e7bdd4da3c5ef966be6043.tar.gz yosys-6d77236f3845cd8785e7bdd4da3c5ef966be6043.tar.bz2 yosys-6d77236f3845cd8785e7bdd4da3c5ef966be6043.zip | |
substr() -> compare()
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/firrtl/firrtl.cc | 2 | ||||
| -rw-r--r-- | backends/intersynth/intersynth.cc | 2 | ||||
| -rw-r--r-- | backends/smt2/smt2.cc | 2 | ||||
| -rw-r--r-- | backends/smv/smv.cc | 2 | ||||
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 4 |
5 files changed, 6 insertions, 6 deletions
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 5be6d60fd..73b1e7d53 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -363,7 +363,7 @@ struct FirrtlWorker } // Check for subfield assignment. std::string bitsString = "bits("; - if (sinkExpr.substr(0, bitsString.length()) == bitsString ) { + if (sinkExpr.compare(0, bitsString.length(), bitsString) == 0) { if (sinkSig == nullptr) log_error("Unknown subfield %s.%s\n", cell_type.c_str(), sinkExpr.c_str()); // Don't generate the assignment here. diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 98746809c..809a0fa09 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -108,7 +108,7 @@ struct IntersynthBackend : public Backend { if (f.fail()) log_error("Can't open lib file `%s'.\n", filename.c_str()); RTLIL::Design *lib = new RTLIL::Design; - Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog"); + Frontend::frontend_call(lib, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "ilang" : "verilog")); libs.push_back(lib); } diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index db849882e..081dcda99 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -1476,7 +1476,7 @@ struct Smt2Backend : public Backend { int indent = 0; while (indent < GetSize(line) && (line[indent] == ' ' || line[indent] == '\t')) indent++; - if (line.substr(indent, 2) == "%%") + if (line.compare(indent, 2, "%%") == 0) break; *f << line << std::endl; } diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc index e9586fae0..f755307bf 100644 --- a/backends/smv/smv.cc +++ b/backends/smv/smv.cc @@ -61,7 +61,7 @@ struct SmvWorker { string name = stringf("_%s", id.c_str()); - if (name.substr(0, 2) == "_\\") + if (name.compare(0, 2, "_\\") == 0) name = "_" + name.substr(2); for (auto &c : name) { diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 6065a71ff..7b1db4776 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -604,7 +604,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type.substr(0, 6) == "$_DFF_") + if (cell->type.begins_with("$_DFF_")) { std::string reg_name = cellname(cell); bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); @@ -645,7 +645,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } - if (cell->type.substr(0, 8) == "$_DFFSR_") + if (cell->type.begins_with("$_DFFSR_")) { char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10]; |