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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:23:37 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:23:37 -0700 |
commit | a6bc9265fbb2abad73120a068a09f0c7833304de (patch) | |
tree | c5fa392fb6b1cf197fcc9e90ae25273e1a8a882c /backends | |
parent | 046e1a52147dd4a0e1f23e4aa7cb71b0a4d1b497 (diff) | |
download | yosys-a6bc9265fbb2abad73120a068a09f0c7833304de.tar.gz yosys-a6bc9265fbb2abad73120a068a09f0c7833304de.tar.bz2 yosys-a6bc9265fbb2abad73120a068a09f0c7833304de.zip |
RTLIL::S{0,1} -> State::S{0,1}
Diffstat (limited to 'backends')
-rw-r--r-- | backends/aiger/xaiger.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index a3a753912..615854459 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -388,11 +388,11 @@ struct XAigerWriter RTLIL::SigSpec rhs; if (it != cell->connections_.end()) { if (GetSize(it->second) < GetSize(w)) - it->second.append(RTLIL::SigSpec(RTLIL::S0, GetSize(w)-GetSize(it->second))); + it->second.append(RTLIL::SigSpec(State::S0, GetSize(w)-GetSize(it->second))); rhs = it->second; } else { - rhs = RTLIL::SigSpec(RTLIL::S0, GetSize(w)); + rhs = RTLIL::SigSpec(State::S0, GetSize(w)); cell->setPort(port_name, rhs); } @@ -400,10 +400,10 @@ struct XAigerWriter for (auto b : rhs.bits()) { SigBit I = sigmap(b); if (b == RTLIL::Sx) - b = RTLIL::S0; + b = State::S0; else if (I != b) { if (I == RTLIL::Sx) - alias_map[b] = RTLIL::S0; + alias_map[b] = State::S0; else alias_map[b] = I; } @@ -672,7 +672,7 @@ struct XAigerWriter if (holes_cell) port_wire.append(holes_wire); else - holes_module->connect(holes_wire, RTLIL::S0); + holes_module->connect(holes_wire, State::S0); } if (!port_wire.empty()) holes_cell->setPort(w->name, port_wire); |