Merge remote-tracking branch 'origin/master' into xaig_dff

3 files changed, 34 insertions, 15 deletions

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 632a5c8d5..a1085addf 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -21,13 +21,15 @@
 // https://stackoverflow.com/a/46137633
 #ifdef _MSC_VER
 #include <stdlib.h>
-#define __builtin_bswap32 _byteswap_ulong
+#define bswap32 _byteswap_ulong
 #elif defined(__APPLE__)
 #include <libkern/OSByteOrder.h>
-#define __builtin_bswap32 OSSwapInt32
-#elif !defined(__GNUC__)
+#define bswap32 OSSwapInt32
+#elif defined(__GNUC__)
+#define bswap32 __builtin_bswap32
+#else
 #include <cstdint>
-inline uint32_t __builtin_bswap32(uint32_t x)
+inline static uint32_t bswap32(uint32_t x)
 {
 	// https://stackoverflow.com/a/27796212
 	register uint32_t value = number_to_be_reversed;
@@ -145,6 +147,7 @@ struct XAigerWriter
 	{
 		pool<SigBit> undriven_bits;
 		pool<SigBit> unused_bits;
+		pool<SigBit> keep_bits;
 
 		// promote public wires
 		for (auto wire : module->wires())
@@ -183,6 +186,9 @@ struct XAigerWriter
 					unused_bits.insert(bit);
 				}
 
+				if (keep)
+					keep_bits.insert(bit);
+
 				if (wire->port_input || keep) {
 					if (bit != wirebit)
 						alias_map[bit] = wirebit;
@@ -260,7 +266,7 @@ struct XAigerWriter
 				continue;
 			}
 
-			RTLIL::Module* inst_module = !holes_mode ? module->design->module(cell->type) : nullptr;
+			RTLIL::Module* inst_module = module->design->module(cell->type);
 			if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
 				abc_box_seen = true;
 
@@ -319,10 +325,11 @@ struct XAigerWriter
 				}
 			}
 			else {
+				bool cell_known = cell->known();
 				for (const auto &c : cell->connections()) {
 					if (c.second.is_fully_const()) continue;
-					auto is_input = cell->input(c.first);
-					auto is_output = cell->output(c.first);
+					auto is_input = !cell_known || cell->input(c.first);
+					auto is_output = !cell_known || cell->output(c.first);
 					if (!is_input && !is_output)
 						log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
 
@@ -330,12 +337,15 @@ struct XAigerWriter
 						for (auto b : c.second.bits()) {
 							Wire *w = b.wire;
 							if (!w) continue;
-							if (!w->port_output) {
+							if (!w->port_output || !cell_known) {
 								SigBit I = sigmap(b);
 								if (I != b)
 									alias_map[b] = I;
 								output_bits.insert(b);
 								unused_bits.erase(b);
+
+								if (!cell_known)
+									keep_bits.insert(b);
 							}
 						}
 					}
@@ -488,7 +498,7 @@ struct XAigerWriter
 
 							auto jt = input_bits.find(b);
 							if (jt != input_bits.end()) {
-								log_assert(b.wire->attributes.count("\\keep"));
+								log_assert(keep_bits.count(O));
 								input_bits.erase(b);
 							}
 						}
@@ -508,7 +518,7 @@ struct XAigerWriter
 			// with $inout.out suffix, make it a PO driven by the existing inout, and
 			// inherit existing inout's drivers
 			if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
-					|| wire->attributes.count("\\keep")) {
+					|| keep_bits.count(bit)) {
 				RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
 				RTLIL::Wire *new_wire = module->wire(wire_name);
 				if (!new_wire)
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index b4ba2b03f..313af7d5c 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -204,6 +204,11 @@ void ILANG_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const
 
 	for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it)
 	{
+		for (auto ait = (*it)->attributes.begin(); ait != (*it)->attributes.end(); ++ait) {
+			f << stringf("%s  attribute %s ", indent.c_str(), ait->first.c_str());
+			dump_const(f, ait->second);
+			f << stringf("\n");
+		}
 		f << stringf("%s  case ", indent.c_str());
 		for (size_t i = 0; i < (*it)->compare.size(); i++) {
 			if (i > 0)
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 827af5d85..087c6fec6 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -364,20 +364,22 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 	}
 }
 
-void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, char term = '\n', bool modattr = false)
+void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString, RTLIL::Const> &attributes, char term = '\n', bool modattr = false, bool as_comment = false)
 {
 	if (noattr)
 		return;
+	if (attr2comment)
+		as_comment = true;
 	for (auto it = attributes.begin(); it != attributes.end(); ++it) {
-		f << stringf("%s" "%s %s", indent.c_str(), attr2comment ? "/*" : "(*", id(it->first).c_str());
+		f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str());
 		f << stringf(" = ");
 		if (modattr && (it->second == Const(0, 1) || it->second == Const(0)))
 			f << stringf(" 0 ");
 		else if (modattr && (it->second == Const(1, 1) || it->second == Const(1)))
 			f << stringf(" 1 ");
 		else
-			dump_const(f, it->second, -1, 0, false, attr2comment);
-		f << stringf(" %s%c", attr2comment ? "*/" : "*)", term);
+			dump_const(f, it->second, -1, 0, false, as_comment);
+		f << stringf(" %s%c", as_comment ? "*/" : "*)", term);
 	}
 }
 
@@ -1492,12 +1494,14 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 		return;
 	}
 
+	dump_attributes(f, indent, sw->attributes);
 	f << stringf("%s" "casez (", indent.c_str());
 	dump_sigspec(f, sw->signal);
 	f << stringf(")\n");
 
 	bool got_default = false;
 	for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
+		dump_attributes(f, indent + "  ", (*it)->attributes, '\n', /*modattr=*/false, /*as_comment=*/true);
 		if ((*it)->compare.size() == 0) {
 			if (got_default)
 				continue;
@@ -1662,7 +1666,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		}
 	}
 
-	dump_attributes(f, indent, module->attributes, '\n', true);
+	dump_attributes(f, indent, module->attributes, '\n', /*attr2comment=*/true);
 	f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
 	bool keep_running = true;
 	for (int port_id = 1; keep_running; port_id++) {