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* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* write_verilog: handle the $shift cell.whitequark2018-12-161-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation corresponds to the following Verilog, which is lifted straight from simlib.v: module \\$shift (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 0; parameter B_WIDTH = 0; parameter Y_WIDTH = 0; input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; generate if (B_SIGNED) begin:BLOCK1 assign Y = $signed(B) < 0 ? A << -B : A >> B; end else begin:BLOCK2 assign Y = A >> B; end endgenerate endmodule
* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-161-1/+1
|\ | | | | select: print selection if a -assert-* flag causes an error
| * write_verilog: add a missing newline.whitequark2018-12-161-1/+1
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* | write_verilog: correctly map RTLIL `sync init`.whitequark2018-12-071-0/+2
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* adding offset info to memoriesrafaeltp2018-10-181-1/+1
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* adding offset info to memoriesrafaeltp2018-10-181-2/+3
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* Fixed typo in "verilog_write" help messageacw12512018-09-181-3/+3
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* Add $lut support to Verilog back-endClifford Wolf2018-09-061-0/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Add $dlatch support to write_verilogClifford Wolf2018-04-221-0/+38
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $shiftx support to verilog front-endClifford Wolf2017-10-071-0/+17
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* Rename "write_verilog -nobasenradix" to "write_verilog -decimal"Clifford Wolf2017-10-031-16/+13
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* Fixed wrong declaration in Verilog backenddh732017-10-011-3/+3
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* Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵dh732017-10-011-3/+16
| | | | M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-4/+6
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* Cleanups and fixed in write_verilog regarding reg initClifford Wolf2016-11-161-15/+61
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* Added hex constant support to write_verilogClifford Wolf2016-11-031-4/+62
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* Adde "write_verilog -renameprefix -v"Clifford Wolf2016-11-011-5/+23
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* Bugfix in partial mem write handling in verilog back-endClifford Wolf2016-08-201-42/+26
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* Added missing support for mem read enable ports to verilog back-endClifford Wolf2016-08-181-6/+14
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* Fixed upto handling in verilog back-endClifford Wolf2016-08-151-0/+3
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* Added "write_verilog -defparam"Clifford Wolf2016-07-301-2/+21
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* Added "write_verilog -nodec -nostr"Clifford Wolf2016-07-301-4/+27
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* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
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* Bugfix in write_verilog for RTLIL processesClifford Wolf2016-03-141-9/+20
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* Bugfixes in writing of memories as VerilogClifford Wolf2015-09-251-7/+8
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* Another block of spelling fixesLarry Doolittle2015-08-141-2/+2
| | | | Smaller this time
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-3/+3
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* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
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* Fixed trailing whitespacesClifford Wolf2015-07-021-4/+4
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* $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-081-54/+108
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* Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-041-14/+16
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* Some fixes for $mem in verilog back-endClifford Wolf2015-05-201-19/+23
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* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-111-1/+2
|\ | | | | Fixed bug in $mem cell verilog code generation.
| * Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-111-11/+12
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* | Disabled broken $mem support in verilog backendClifford Wolf2015-05-101-11/+11
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* Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-101-22/+11
| | | | | | Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used dict<> instead of std::map, and used RTLIL::SigSpec instead of std::vector.
* Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-081-50/+105
| | | | write-enable bits and RD_TRANSPARENT parameter settings.
* Added support for $mem cells in the verilog backend.luke whittlesey2015-05-071-1/+120
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* Minor fixes in handling of "init" attributeClifford Wolf2015-04-091-7/+7
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* Added "init" attribute support to verilog backendClifford Wolf2015-04-041-0/+5
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* Added Verilog backend $dffsr supportClifford Wolf2015-03-181-1/+51
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* Fixed "write_verilog -attr2comment" handling of "*/" in stringsClifford Wolf2015-02-131-2/+4
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* Added dict/pool.sort()Clifford Wolf2015-01-241-0/+2
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* Cosmetic changes in verilog output formatClifford Wolf2015-01-021-5/+10
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* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-261-25/+25
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-1/+1
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* Added $dffe support to write_verilogClifford Wolf2014-12-201-3/+14
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* Fixed generation of temp names in verilog backendClifford Wolf2014-11-071-4/+5
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