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* verilog_backend: Do not run bwmuxmap even if in expr modeJannis Harder2023-02-131-1/+0
| | | | | While bwmuxmap generates equivalent logic, it doesn't propagate x bits in the same way, which can be relevant when writing verilog.
* Add bwmuxmap passJannis Harder2022-11-301-0/+1
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* verilog_backend: Do not run bmuxmap or demuxmap in -noexpr mode.Jannis Harder2022-11-301-2/+4
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* verilog_backend: Correctly sign extend output of signed `$modfloor`Jannis Harder2022-11-301-2/+2
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* verilog_backend: Add -noparallelcase optionJannis Harder2022-11-301-7/+31
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* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-1/+2
| | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
* verilog backend: Emit a `wire` for ports as well.Marcelina Kościelnicka2022-01-311-1/+1
| | | | Fixes #3177.
* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-281-0/+4
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* Add clean_zerowidth pass, use it for Verilog output.Marcelina Kościelnicka2021-12-121-0/+2
| | | | | | | This should remove instances of zero-width sigspecs in the netlist, avoiding problems in the Verilog backend with emitting them. See #3103.
* write_verilog: dump zero width sigspecs correctly.whitequark2021-12-111-1/+2
| | | | | | | | | | | | | Before this commit, zero width sigspecs were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) PR #1203 has addressed this issue before, but in an incomplete way.
* Give initial wire unique ID, fixes #2914Miodrag Milanovic2021-11-171-4/+6
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* Split module ports, 20 per lineMiodrag Milanovic2021-10-091-0/+2
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* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-021-43/+70
| | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-111-9/+9
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* backend/verilog: Add alternate mode for transparent read port output.Marcelina Kościelnicka2021-08-011-1/+71
| | | | | | This mode will be used whenever read port cannot be handled in the "extract address register" way, ie. whenever it has enable, reset, init functionality or (in the future) mixed transparency mask.
* backends/verilog: Support meminit with mask.Marcelina Kościelnicka2021-07-281-3/+18
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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* backends/verilog: Add support for memory read port reset and init value.Marcelina Kościelnicka2021-05-271-9/+81
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* backends/verilog: Add wide port support.Marcelina Kościelnicka2021-05-271-43/+88
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* backends/verilog: Try to preserve mem write port priorities.Marcelina Kościelnicka2021-05-261-32/+84
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* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-221-1/+1
| | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list.
* Add verilog backend option for simple_lhsMiodrag Milanovic2020-11-251-6/+22
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* generate only simple assignments in verilog backendMiodrag Milanovic2020-11-251-5/+9
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* verilog_backend: Use Mem helper.Marcelina Kościelnicka2020-10-211-274/+251
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* write_verilog: emit intermediate wire for constant values in sensitivity listN. Engelhardt2020-09-281-7/+53
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* Respect \A_SIGNED for $shiftXiretza2020-08-181-6/+4
| | | | | | This reflects the behaviour of $shr/$shl, which sign-extend their A operands to the size of their output, then do a logical shift (shift in 0-bits).
* verilog_backend: Add handling for all FF types.Marcelina Kościelnicka2020-07-301-252/+134
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* verilog_backend: in non-SV mode, add a trigger for `always @*`.whitequark2020-07-161-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | This commit only affects translation of RTLIL processes (for which there is limited support). Due to the event-driven nature of Verilog, processes like reg x; always @* x <= 1; may never execute. This can be fixed in SystemVerilog code by using `always_comb` instead of `always @*`, but in Verilog-2001 the options are limited. This commit implements the following workaround: reg init = 0; reg x; always @* begin if (init) begin end x <= 1; end Fixes #2271.
* verilog_backend: add `-sv` option, make `-o <filename>.sv` work.whitequark2020-07-161-11/+18
| | | | See #2271.
* Use C++11 final/override keywords.whitequark2020-06-181-2/+2
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* Add flooring division operatorXiretza2020-05-281-0/+55
| | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* Add flooring modulo operatorXiretza2020-05-281-0/+34
| | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* write_verilog: fix precondition check.whitequark2020-04-141-1/+1
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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-221/+221
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* kernel: use more ID::*Eddie Hung2020-04-021-41/+41
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* Clean up pseudo-private member usage in `backends/verilog/verilog_backend.cc`.Alberto Gonzalez2020-04-011-22/+19
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* specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-2/+10
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* write_verilog: dump $mem cell attributes.whitequark2020-02-061-0/+1
| | | | | The Verilog backend already dumps attributes on RTLIL::Memory objects but not on `$mem` cells.
* write_verilog: add -extmem option, to write split memory init files.whitequark2019-11-181-10/+80
| | | | | Some toolchains (in particular Quartus) are pathologically slow if a large amount of assignments in `initial` blocks are used.
* write_verilog: do not print (*init*) attributes on regs.whitequark2019-09-221-4/+5
| | | | | | | | | | If an init value is emitted for a reg, an (*init*) attribute is never necessary, since it is exactly equivalent. On the other hand, some tools that consume Verilog (ISE, Vivado, Quartus) complain about (*init*) attributes because their interpretation differs from Yosys. All (*init*) attributes that would not become reg init values anyway are emitted as before.
* substr() -> compare()Eddie Hung2019-08-071-2/+2
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* RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-6/+6
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* Use State::S{0,1}Eddie Hung2019-08-061-2/+2
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* Make liberal use of IdString.in()Eddie Hung2019-08-061-1/+1
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* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1203 from whitequark/write_verilog-zero-width-valuesClifford Wolf2019-07-181-1/+2
|\ | | | | write_verilog: dump zero width constants correctly
| * write_verilog: dump zero width constants correctly.whitequark2019-07-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, zero width constants were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) Fixes #948 (again).
* | Remove old $pmux_safe code from write_verilogClifford Wolf2019-07-171-5/+4
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmarkClifford Wolf2019-07-111-2/+8
|\ | | | | write_verilog: write RTLIL::Sa aka - as Verilog ?
| * write_verilog: write RTLIL::Sa aka - as Verilog ?.whitequark2019-07-091-2/+8
| | | | | | | | | | | | | | Currently, the only ways (determined by grepping for regex \bSa\b) to end up with RTLIL::Sa in a netlist is by reading a Verilog constant with ? in it as a part of case, or by running certain FSM passes. Both of these cases should be round-tripped back to ? in Verilog.
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