diff options
| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-22 19:14:13 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-22 21:43:00 +0200 |
| commit | c4cc888b2c51a6507b73fdcde1dc61c37384105d (patch) | |
| tree | d5bc86b7ae97217a242c7e1f5b6f9ad6da1e4c7d /backends/verilog | |
| parent | c7076495f197732725456992c9a02aed9966139a (diff) | |
| download | yosys-c4cc888b2c51a6507b73fdcde1dc61c37384105d.tar.gz yosys-c4cc888b2c51a6507b73fdcde1dc61c37384105d.tar.bz2 yosys-c4cc888b2c51a6507b73fdcde1dc61c37384105d.zip | |
kernel/rtlil: Extract some helpers for checking memory cell types.
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 165ce1ea4..cfdc0316a 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1464,7 +1464,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell) { // Handled by dump_memory - if (cell->type.in(ID($mem), ID($memwr), ID($memrd), ID($meminit))) + if (cell->is_mem_cell()) return; if (cell->type[0] == '$' && !noexpr) { |