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| author | Xiretza <xiretza@xiretza.xyz> | 2020-07-03 13:13:21 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-18 19:36:24 +0200 |
| commit | 928fd40c2ebc8b83b76c02d80d751d2531341d9d (patch) | |
| tree | 7bc53f51a0c374c33549c07bf952eb01716bd20e /backends/verilog | |
| parent | 22765ef0a5ff5af9f6efae9b5443afa7bccfb4e5 (diff) | |
| download | yosys-928fd40c2ebc8b83b76c02d80d751d2531341d9d.tar.gz yosys-928fd40c2ebc8b83b76c02d80d751d2531341d9d.tar.bz2 yosys-928fd40c2ebc8b83b76c02d80d751d2531341d9d.zip | |
Respect \A_SIGNED for $shift
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index a0e677d13..372f68ea5 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -750,21 +750,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf(" = "); if (cell->getParam(ID::B_SIGNED).as_bool()) { - f << stringf("$signed("); - dump_sigspec(f, cell->getPort(ID::B)); - f << stringf(")"); + dump_cell_expr_port(f, cell, "B", true); f << stringf(" < 0 ? "); - dump_sigspec(f, cell->getPort(ID::A)); + dump_cell_expr_port(f, cell, "A", true); f << stringf(" << - "); dump_sigspec(f, cell->getPort(ID::B)); f << stringf(" : "); - dump_sigspec(f, cell->getPort(ID::A)); + dump_cell_expr_port(f, cell, "A", true); f << stringf(" >> "); dump_sigspec(f, cell->getPort(ID::B)); } else { - dump_sigspec(f, cell->getPort(ID::A)); + dump_cell_expr_port(f, cell, "A", true); f << stringf(" >> "); dump_sigspec(f, cell->getPort(ID::B)); } |