diff options
| author | whitequark <whitequark@whitequark.org> | 2020-02-06 16:22:22 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-02-06 16:22:42 +0000 |
| commit | e95a8ba763999b9cce480a3aadf9fae206650f00 (patch) | |
| tree | 6fbe88d0c6614f26dca9e8dcfeffbe5bd8caf91b /backends/verilog | |
| parent | d44848328b329489eda0719968c3f81d4d9a6b55 (diff) | |
| download | yosys-e95a8ba763999b9cce480a3aadf9fae206650f00.tar.gz yosys-e95a8ba763999b9cce480a3aadf9fae206650f00.tar.bz2 yosys-e95a8ba763999b9cce480a3aadf9fae206650f00.zip | |
write_verilog: dump $mem cell attributes.
The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 54d0f6148..682c47a1f 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1066,6 +1066,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) // initial begin // memid[0] = ... // end + dump_attributes(f, indent.c_str(), cell->attributes); f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size+offset-1, offset); if (use_init) { |