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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-01-24 16:02:29 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-01-28 23:34:41 +0100 |
| commit | 93508d58dafbbffcedffa70b21a197b6fca8bb30 (patch) | |
| tree | 4f4bed22749559a1938457015ff875891fd7a40a /backends/verilog | |
| parent | db33b1e535f5ee93dba9ee1cc181b91c482a4dee (diff) | |
| download | yosys-93508d58dafbbffcedffa70b21a197b6fca8bb30.tar.gz yosys-93508d58dafbbffcedffa70b21a197b6fca8bb30.tar.bz2 yosys-93508d58dafbbffcedffa70b21a197b6fca8bb30.zip | |
Add $bmux and $demux cells.
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index e4781ef3e..32003cf54 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -2300,7 +2300,11 @@ struct VerilogBackend : public Backend { extmem_prefix = filename.substr(0, filename.rfind('.')); } + log_push(); + Pass::call(design, "bmuxmap"); + Pass::call(design, "demuxmap"); Pass::call(design, "clean_zerowidth"); + log_pop(); design->sort(); |