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* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
* write_verilog: handle the $shift cell.whitequark2018-12-161-0/+29
* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-161-1/+1
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| * write_verilog: add a missing newline.whitequark2018-12-161-1/+1
* | write_verilog: correctly map RTLIL `sync init`.whitequark2018-12-071-0/+2
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* adding offset info to memoriesrafaeltp2018-10-181-1/+1
* adding offset info to memoriesrafaeltp2018-10-181-2/+3
* Fixed typo in "verilog_write" help messageacw12512018-09-181-3/+3
* Add $lut support to Verilog back-endClifford Wolf2018-09-061-0/+13
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Add $dlatch support to write_verilogClifford Wolf2018-04-221-0/+38
* Add $shiftx support to verilog front-endClifford Wolf2017-10-071-0/+17
* Rename "write_verilog -nobasenradix" to "write_verilog -decimal"Clifford Wolf2017-10-031-16/+13
* Fixed wrong declaration in Verilog backenddh732017-10-011-3/+3
* Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ...dh732017-10-011-3/+16
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-4/+6
* Cleanups and fixed in write_verilog regarding reg initClifford Wolf2016-11-161-15/+61
* Added hex constant support to write_verilogClifford Wolf2016-11-031-4/+62
* Adde "write_verilog -renameprefix -v"Clifford Wolf2016-11-011-5/+23
* Bugfix in partial mem write handling in verilog back-endClifford Wolf2016-08-201-42/+26
* Added missing support for mem read enable ports to verilog back-endClifford Wolf2016-08-181-6/+14
* Fixed upto handling in verilog back-endClifford Wolf2016-08-151-0/+3
* Added "write_verilog -defparam"Clifford Wolf2016-07-301-2/+21
* Added "write_verilog -nodec -nostr"Clifford Wolf2016-07-301-4/+27
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Bugfix in write_verilog for RTLIL processesClifford Wolf2016-03-141-9/+20
* Bugfixes in writing of memories as VerilogClifford Wolf2015-09-251-7/+8
* Another block of spelling fixesLarry Doolittle2015-08-141-2/+2
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-3/+3
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-4/+4
* $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-081-54/+108
* Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-041-14/+16
* Some fixes for $mem in verilog back-endClifford Wolf2015-05-201-19/+23
* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-111-1/+2
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| * Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-111-11/+12
* | Disabled broken $mem support in verilog backendClifford Wolf2015-05-101-11/+11
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* Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-101-22/+11
* Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-081-50/+105
* Added support for $mem cells in the verilog backend.luke whittlesey2015-05-071-1/+120
* Minor fixes in handling of "init" attributeClifford Wolf2015-04-091-7/+7
* Added "init" attribute support to verilog backendClifford Wolf2015-04-041-0/+5
* Added Verilog backend $dffsr supportClifford Wolf2015-03-181-1/+51
* Fixed "write_verilog -attr2comment" handling of "*/" in stringsClifford Wolf2015-02-131-2/+4
* Added dict/pool.sort()Clifford Wolf2015-01-241-0/+2
* Cosmetic changes in verilog output formatClifford Wolf2015-01-021-5/+10
* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-261-25/+25
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-1/+1
* Added $dffe support to write_verilogClifford Wolf2014-12-201-3/+14
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