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* Bugfixes in writing of memories as VerilogClifford Wolf2015-09-251-7/+8
* Another block of spelling fixesLarry Doolittle2015-08-141-2/+2
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-3/+3
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-4/+4
* $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-081-54/+108
* Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-041-14/+16
* Some fixes for $mem in verilog back-endClifford Wolf2015-05-201-19/+23
* Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-111-1/+2
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| * Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-111-11/+12
* | Disabled broken $mem support in verilog backendClifford Wolf2015-05-101-11/+11
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* Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-101-22/+11
* Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-081-50/+105
* Added support for $mem cells in the verilog backend.luke whittlesey2015-05-071-1/+120
* Minor fixes in handling of "init" attributeClifford Wolf2015-04-091-7/+7
* Added "init" attribute support to verilog backendClifford Wolf2015-04-041-0/+5
* Added Verilog backend $dffsr supportClifford Wolf2015-03-181-1/+51
* Fixed "write_verilog -attr2comment" handling of "*/" in stringsClifford Wolf2015-02-131-2/+4
* Added dict/pool.sort()Clifford Wolf2015-01-241-0/+2
* Cosmetic changes in verilog output formatClifford Wolf2015-01-021-5/+10
* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-261-25/+25
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-1/+1
* Added $dffe support to write_verilogClifford Wolf2014-12-201-3/+14
* Fixed generation of temp names in verilog backendClifford Wolf2014-11-071-4/+5
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-1/+1
* namespace YosysClifford Wolf2014-09-272-42/+3
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-061-1/+2
* Removed $bu0 cell typeClifford Wolf2014-09-041-1/+0
* Using $pos models for $bu0Clifford Wolf2014-09-031-16/+1
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-232-233/+232
* Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-161-4/+4
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-161-4/+40
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-1/+1
* Refactoring of CellType classClifford Wolf2014-08-141-10/+28
* Be more conservative with printing decimal numbers in verilog backendClifford Wolf2014-08-021-2/+3
* Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-021-3/+19
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-6/+6
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-40/+40
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-281-9/+22
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-3/+2
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-3/+3
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-4/+4
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-2/+2
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-4/+4
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-43/+43
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-43/+43
* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-251-21/+29
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-231-3/+0
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-2/+2
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