iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added "int ceil_log2(int)" function	Clifford Wolf	2016-02-13	5	-10/+58
*	Run dffsr2dff in synth_xilinx	Clifford Wolf	2016-02-13	1	-0/+2
*	Support for more Verific primitives (patch I got per email)	Clifford Wolf	2016-02-13	1	-1/+31
*	Updated ABC	Clifford Wolf	2016-02-08	1	-1/+1
*	Work around DDR dout sim glitches in ice40 SB_IO sim model	Clifford Wolf	2016-02-07	1	-1/+7
*	Updated ABC	Clifford Wolf	2016-02-07	1	-1/+1
*	Added "stat -liberty" for calculating chip area	Clifford Wolf	2016-02-04	1	-6/+60
*	Bugfix in Verific front-end	Clifford Wolf	2016-02-03	1	-2/+5
*	Updated verific build instructions	Clifford Wolf	2016-02-02	1	-2/+0
*	Improved dffsr2dff pass	Clifford Wolf	2016-02-02	1	-5/+50
*	Added dffsr2dff	Clifford Wolf	2016-02-02	3	-0/+171
*	Added addBufGate module method	Clifford Wolf	2016-02-02	3	-0/+8
*	Use alphanumerical order instead of idstring idx in opt_clean compare_signals()	Clifford Wolf	2016-02-02	1	-1/+1
*	Added CodeOfConduct	Clifford Wolf	2016-02-01	1	-0/+73
*	Updated ABC to hg rev ee212a9e94df	Clifford Wolf	2016-02-01	1	-1/+1
*	Progress in cell library documentation	Clifford Wolf	2016-02-01	1	-0/+238
*	Added "abc -luts" option, Improved Xilinx logic mapping	Clifford Wolf	2016-02-01	2	-15/+39
*	Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)	Clifford Wolf	2016-02-01	1	-8/+68
*	SigMap performance improvement	Clifford Wolf	2016-02-01	1	-1/+7
*	hashlib mfp<> performance improvements	Clifford Wolf	2016-02-01	1	-2/+7
*	Added reserve() method to haslib classes and	Clifford Wolf	2016-01-31	1	-2/+6
*	Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys	Clifford Wolf	2016-01-31	2	-14/+88
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\| *	rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)	Rick Altherr	2016-01-31	1	-2/+31
\| *	rtlil: speed up SigSpec::sort_and_unify()	Rick Altherr	2016-01-31	1	-1/+11
\| *	rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)	Rick Altherr	2016-01-31	1	-6/+14
\| *	genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSi...	Rick Altherr	2016-01-31	1	-3/+3
\| *	rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)	Rick Altherr	2016-01-31	1	-2/+29
* \|	More clang sanitizer stuff	Clifford Wolf	2016-01-31	2	-3/+12
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*	Meaningless coding style change	Clifford Wolf	2016-01-31	1	-1/+0
*	Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys	Clifford Wolf	2016-01-31	2	-23/+37
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\| *	rtlil: rewrite remove2() to avoid copying	Rick Altherr	2016-01-30	1	-45/+18
\| *	rtlil: duplicate remove2() for std::set<>	Rick Altherr	2016-01-29	2	-0/+41
\| *	rtlil: change IdString comparison operators to take references instead of copies	Rick Altherr	2016-01-29	1	-3/+3
* \|	Addedd clang sanitizers	Clifford Wolf	2016-01-31	1	-0/+21
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*	Added "equiv_struct -fwonly"	Clifford Wolf	2016-01-08	1	-5/+17
*	Bugfixes in equiv_struct	Clifford Wolf	2016-01-08	1	-2/+9
*	Added "submod -copy"	Clifford Wolf	2016-01-08	1	-13/+28
*	Added "write_blif -cname" mode	Clifford Wolf	2016-01-06	1	-1/+12
*	Added "equiv_struct -maxiter <N>"	Clifford Wolf	2016-01-06	1	-4/+16
*	Added "equiv_add -try" mode	Clifford Wolf	2016-01-06	1	-6/+33
*	Fixed "splitnets -ports" for hierarchical designs	Clifford Wolf	2015-12-22	1	-0/+57
*	Re-run ice40_opt in "synth_ice40 -abc2"	Clifford Wolf	2015-12-22	1	-1/+4
*	Improvements in ice40_opt	Clifford Wolf	2015-12-22	1	-5/+16
*	Bugfix in ice40_ffinit	Clifford Wolf	2015-12-22	1	-2/+2
*	Improved ice40_ffinit	Clifford Wolf	2015-12-22	1	-1/+22
*	Run opt_const before check in default scripts	Clifford Wolf	2015-12-22	2	-0/+4
*	Added %R select expression	Clifford Wolf	2015-12-20	1	-0/+50
*	Various improvements in BLIF front-end	Clifford Wolf	2015-12-20	2	-41/+86
*	Added yosys-smtbmc -S	Clifford Wolf	2015-12-20	1	-6/+35
*	Merge pull request #110 from scanlime/master	Clifford Wolf	2015-12-15	2	-2/+2
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