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* Add support for GHDL modfloor operatorMichael Nolan2022-07-052-1/+22
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* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-282-1/+53
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* cxxrtl: don't reset elided wires with \init attribute.Catherine2021-12-251-0/+2
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* cxxrtl: demote wires not inlinable only in debug_eval to locals.Catherine2021-12-151-3/+4
| | | | | | Fixes #3112. Co-authored-by: Irides <irides@irides.network>
* cxxrtl: preserve interior memory pointers across reset.Catherine2021-12-112-95/+67
| | | | | | | | Before this commit, values, wires, and memories with an initializer were value-initialized in emitted C++ code. After this commit, all values, wires, and memories are default-initialized, and the default constructor of generated modules calls the reset() method, which assigns the members that have an initializer.
* cxxrtl: use unique_ptr<value<>[]> to store memory contents.whitequark2021-12-111-16/+16
| | | | This makes the depth properly immutable.
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-021-1/+16
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* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-111-18/+21
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* Merge pull request #2885 from whitequark/cxxrtl-fix-2883whitequark2021-07-201-2/+8
|\ | | | | cxxrtl: treat wires with multiple defs as not inlinable
| * cxxrtl: treat wires with multiple defs as not inlinable.whitequark2021-07-201-2/+8
| | | | | | | | Fixes #2883.
* | cxxrtl: treat assignable internal wires used only for debug as locals.whitequark2021-07-201-10/+12
|/ | | | | | This issue was introduced in commit 4aa65f40 while fixing #2739. Fixes #2882.
* cxxrtl: escape colon in variable names in VCD writer.whitequark2021-07-191-1/+14
| | | | | | | | | | | | The following VCD file crashes GTKWave's VCD loader: $var wire 1 ! x:1 $end $enddefinitions $end In practice, a colon can be a part of a variable name that is translated from a Verilog function, something like: update$func$.../hdl/hazard3_csr.v:350$2534.$result
* cxxrtl: add debug_item::{get,set}.whitequark2021-07-181-0/+16
| | | | Fixes #2877.
* cxxrtl: treat internal wires used only for debug as constants.whitequark2021-07-171-0/+6
| | | | Fixes #2739 (again).
* Merge pull request #2874 from whitequark/cxxrtl-fix-2589whitequark2021-07-161-9/+6
|\ | | | | cxxrtl: run hierarchy pass regardless of (*top*) attribute presence
| * cxxrtl: run hierarchy pass regardless of (*top*) attribute presence.whitequark2021-07-161-9/+6
| | | | | | | | | | | | | | The hierarchy pass does a lot more than just finding the top module, mainly resolving implicit (positional, wildcard) module connections. Fixes #2589.
* | Merge pull request #2873 from whitequark/cxxrtl-fix-2500whitequark2021-07-161-3/+3
|\ \ | | | | | | cxxrtl: emit debug items for unused public wires
| * | cxxrtl: emit debug items for unused public wires.whitequark2021-07-161-3/+3
| |/ | | | | | | | | | | This greatly improves debug information coverage. Fixes #2500.
* / cxxrtl: don't expect user cell inputs to be wires.whitequark2021-07-161-2/+2
|/ | | | | | Ports can be connected to constants, too. (Usually resets.) Fixes #2521.
* cxxrtl: don't mark buffered internal wires as UNUSED for debug.whitequark2021-07-161-1/+1
| | | | | | | | | | Public wires may alias buffered internal wires, so keep BUFFERED wires in debug information even if they are private. Debug items are only created for public wires, so this does not otherwise affect how debug information is emitted. Fixes #2540. Fixes #2841.
* cxxrtl: mark dead local wires as unused even with inlining disabled.whitequark2021-07-151-4/+6
| | | | Fixes #2739.
* kernel/mem: Add a coalesce_inits helper.Marcelina Kościelnicka2021-07-131-1/+5
| | | | | | | While this helper is already useful to squash sequential initializations into one in cxxrtl, its main purpose is to squash overlapping masked memory initializations (when they land) and avoid having to deal with them in cxxrtl runtime.
* cxxrtl: Support memory writes in processes.Marcelina Kościelnicka2021-07-121-6/+55
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* cxxrtl: Add support for memory read port reset.Marcelina Kościelnicka2021-07-121-1/+41
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* cxxrtl: Add support for mem read port initial data.Marcelina Kościelnicka2021-07-121-4/+22
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* cxxrtl: Convert to Mem helpers.Marcelina Kościelnicka2021-07-121-206/+276
| | | | | This *only* does conversion, but doesn't add any new functionality — support for memory read port init/reset is still upcoming.
* cxxrtl: don't assert on edge sync rules tied to a constant.whitequark2021-03-071-0/+4
| | | | | These are commonly the result of tying an async reset to an inactive level.
* cxxrtl: allow `always` sync rules in debug_eval.whitequark2021-03-071-17/+25
| | | | | These can be produced from `always @*` processes, if `-noproc` is used.
* Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addrwhitequark2021-03-051-1/+3
|\ | | | | cxxrtl: follow aliases to outlines when emitting $memrd.ADDR
| * cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.whitequark2021-03-051-1/+3
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* | Merge pull request #2634 from whitequark/cxxrtl-debug-wire-typeswhitequark2021-03-051-0/+46
|\ \ | | | | | | cxxrtl: add pass debug flag to show assigned wire types
| * | cxxrtl: add pass debug flag to show assigned wire types.whitequark2021-03-051-0/+46
| |/ | | | | | | Refs #2543.
* / cxxrtl: don't crash on empty designs.whitequark2021-03-051-1/+1
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* Merge pull request #2563 from whitequark/cxxrtl-msvcwhitequark2021-01-262-10/+10
|\ | | | | cxxrtl: do not use `->template` for non-dependent names
| * cxxrtl: do not use `->template` for non-dependent names.whitequark2021-01-262-10/+10
| | | | | | | | This breaks build on MSVC but not GCC/Clang.
* | Improves the previous commit with a more complete coverage of the casesIris Johnson2021-01-151-12/+12
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* | Handle sliced bits as clock inputs (fixes #2542)Iris Johnson2021-01-141-3/+11
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* cxxrtl: don't crash generating debug information for unused wires.whitequark2020-12-221-9/+10
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* cxxrtl: split processes into sync and case nodes.whitequark2020-12-221-11/+26
| | | | | | | | | | | Similar to the treatment of black boxes, splitting processes into two scheduling nodes adds sufficient freedom so that netlists with well-behaved processes (e.g. those emitted by nMigen) can immediately converge. Because processes are not emitted into edge-triggered regions, this approach has comparable performance to -O5 (without -noproc), which is substantially slower than -O6.
* cxxrtl: completely rewrite netlist layout code.whitequark2020-12-221-406/+569
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The exact shape of C++ code emitted by CXXRTL has a critical effect on performance, both compile-time and runtime. CXXRTL's performance greatly improved when it started localizing and inlining wires, not only because this assists the optimizer and register allocator, but also because inlining code into edge-triggered regions cuts the time spent in eval() by at least a factor of two. However, the logic of netlist layout has always been ad-hoc, fragile, and very hard to understand and modify. After commit ece25a45, which introduced outlining, the same logic started being applied to two distinct netlists at once instead of one, which barely worked. This commit does four major changes: * There is now a single unambiguous source of truth (per subgraph) for the layout of any emitted wire. * Netlist layout is now done entirely during analysis using well known graph algorithms; no graph operations happen when emitting. * Netlist layout now happens completely separately for eval() and debug_eval() subgraphs. * Unreachable (within subgraph scope) netlist nodes are now neither emitted nor considered for wire inlining decisions. The netlist layout code should also now closely match the described semantics. As a part of this large cleanup, it includes many miscellaneous improvements: * The "bare minimum" debug level introduced in commit dd6a761d was split into two levels; -g1 now emits debug information *only* for inputs and state wires, and -g2 now emits debug information for all public members. The old behavior matches -g2. This is done to avoid bloat on low optimization levels. * Debug aliases and inlined connections are now handled separately, and complex RHS never interferes with inlined connections. * Aliases to outlined wires now carry a pointer to the outline. * Cell sync outputs can now be emitted in debug_eval(). * Black box debug information now includes comb/sync driver flags. * The comment emitted for inlined cells is now accurate. * Debug information statistics now has less noise. * Netlist layout code is now much better documented. Due to more precise inlining decisions, unmodified (i.e. with no Yosys script being used) netlists now have much more logic inlined into edge-triggered regions. On Minerva SoC SRAM, this improves runtime by 20-25% across compilers and optimization levels. Due to more precise reachability analysis, much less C++ code is now emitted, especially at the maximum debug level. On Minerva SoC SRAM, this improves clang compile time by 30-50% depending on options. gcc is not affected.
* cxxrtl: simplify logic choosing wire type. NFCI.whitequark2020-12-211-19/+8
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* cxxrtl: clarify node use-def construction. NFCI.whitequark2020-12-211-18/+11
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* cxxrtl: fix typo.whitequark2020-12-211-2/+2
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* cxxrtl: speed up bit repeats (sign extends, etc).whitequark2020-12-212-5/+28
| | | | | On Minerva SoC SRAM, depending on the compiler, this change improves overall time by 4-7%.
* cxxrtl: speed up commits on clang.whitequark2020-12-211-3/+3
| | | | | | On Minerva SoC SRAM compiled with clang-11, this change cuts commit time in half (!) and overall time by 20%. When compiled with gcc-10, there is no difference.
* cxxrtl: use `static inline` instead of `inline` in the C API.whitequark2020-12-201-1/+1
| | | | | | In C, non-static inline functions require an implementation elsewhere (even though the body is right there in the header). It is basically never desirable to use those as opposed to static inline ones.
* cxxrtl: print names of cells inlined in connections.whitequark2020-12-151-1/+10
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* cxxrtl: disable optimization of debug_items().whitequark2020-12-152-3/+15
| | | | | | | | | | | | | | | | | | Implementing outlining has greatly increased the amount of debug information in a typical build, and consequently exposed performance issues in C++ compilers, which are similar for both GCC and Clang; the compile time of Minerva SoC SRAM increased almost twofold. Although one would expect the slowdown to be caused by the increased use of templates in `debug_eval()`, it is actually almost entirely attributable to optimizations and codegen for `debug_items()`. Fortunately, it is neither possible nor desirable to optimize `debug_items()`: in most cases it is called exactly once, and its body is a linear sequence of calls with unique arguments. This commit turns off optimizations for `debug_items()` on GCC and Clang, improving -Os compile time of Minerva SoC SRAM by ~40% (!)
* cxxrtl: make alias analysis outlining-aware.whitequark2020-12-151-38/+48
| | | | | | | | | | | | | | | | | | Before this commit, if a sequence of wires assigned in a chain would terminate on a cell, none of the wires would get marked as aliases, and typically all of the public wires would get outlined. The reason for this behavior is that alias analysis predates outlining and in fact runs before it. After this commit, alias analysis runs after outlining and considers outlined wires valid aliasees. More importantly, if the chained wires contain any valid aliasees, then all of the wires are aliased to the one that is topologically deepest. Aliased wires incur virtually no overhead for the VCD writer, unlike outlined wires that would otherwise take their place. On Minerva SoC SRAM, size of the full VCD dump is reduced by ~65%, and throughput is increased by ~55%.
* cxxrtl: add a "bare minimum" debug information level.whitequark2020-12-141-9/+17
| | | | | Useful to reduce overhead when no debug capabilities are necessary except for access to design state.
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