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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-07-10 23:47:01 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-07-12 18:27:48 +0200 |
commit | af7fa62251b101266bf8419ab69e510fe5bc7e08 (patch) | |
tree | 99cbd195b8d151039623b349893cdb04dc2375f0 /backends/cxxrtl | |
parent | be5cf296997a203cdf195d7355426fa4cd187b49 (diff) | |
download | yosys-af7fa62251b101266bf8419ab69e510fe5bc7e08.tar.gz yosys-af7fa62251b101266bf8419ab69e510fe5bc7e08.tar.bz2 yosys-af7fa62251b101266bf8419ab69e510fe5bc7e08.zip |
cxxrtl: Add support for memory read port reset.
Diffstat (limited to 'backends/cxxrtl')
-rw-r--r-- | backends/cxxrtl/cxxrtl_backend.cc | 42 |
1 files changed, 41 insertions, 1 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index b312878c3..2c93c8ad5 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -1600,7 +1600,29 @@ struct CxxrtlWorker { f << " = value<" << mem->width << "> {};\n"; dec_indent(); f << indent << "}\n"; - if (has_enable) { + if (has_enable && !port.ce_over_srst) { + dec_indent(); + f << indent << "}\n"; + } + if (port.srst != State::S0) { + // Synchronous reset + std::vector<const RTLIL::Cell*> inlined_cells_srst; + collect_sigspec_rhs(port.srst, for_debug, inlined_cells_srst); + if (!inlined_cells_srst.empty()) + dump_inlined_cells(inlined_cells_srst); + f << indent << "if ("; + dump_sigspec_rhs(port.srst); + f << " == value<1> {1u}) {\n"; + inc_indent(); + f << indent; + dump_sigspec_lhs(port.data); + f << " = "; + dump_const(port.srst_value); + f << ";\n"; + dec_indent(); + f << indent << "}\n"; + } + if (has_enable && port.ce_over_srst) { dec_indent(); f << indent << "}\n"; } @@ -1608,6 +1630,24 @@ struct CxxrtlWorker { dec_indent(); f << indent << "}\n"; } + if (port.arst != State::S0) { + // Asynchronous reset + std::vector<const RTLIL::Cell*> inlined_cells_arst; + collect_sigspec_rhs(port.arst, for_debug, inlined_cells_arst); + if (!inlined_cells_arst.empty()) + dump_inlined_cells(inlined_cells_arst); + f << indent << "if ("; + dump_sigspec_rhs(port.arst); + f << " == value<1> {1u}) {\n"; + inc_indent(); + f << indent; + dump_sigspec_lhs(port.data); + f << " = "; + dump_const(port.arst_value); + f << ";\n"; + dec_indent(); + f << indent << "}\n"; + } } void dump_mem_wrports(const Mem *mem, bool for_debug = false) |